Method and apparatus for using ATM queues for segmentation and reassembly of data frames

• US 6,201,813 B1
• Filed: 06/30/1997
• Issued: 03/13/2001
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Hughes, David A., Wong, Kevin, Klausmeier, Daniel E.
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US08/884,705
• Time in Patent Office: 1,352 Days
• Field of Search: 370/395, 370/397, 370/399, 370/412, 370/413, 370/415, 370/417, 370/428, 370/429, 370/469, 370/471, 370/474, 370/476, 370/465, 370/235, 370/230, 370/229, 370/236, 370/234, 370/381, 370/396, 370/359, 370/379, 370/389, 370/392, 370/409
• US Class Current: 370/412
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5658 using the AAL5
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A plurality of cells are received from a digital network and stored in a logical queue. The cells contain data information and logical connection information and the logical queue corresponds to the logical connection identified by the logical connection information. The cells are combined into a frame by extracting the cells from the logical queue and storing the cells to a local memory so that the data information is preserved. Extraction may be accomplished by notifying a local processor that the frame'"'"'s worth of data is ready and then transferring the data information of the cells to a local memory at the direction of the local processor. During the transfer, error detection operations may be performed. Information may be transmitted into the digital network by segmenting a frame of data into a plurality of cells and injecting each of the cells into a logical queue. The logical queue may be constructed with a series of linked list pointers associated with the memory locations. The cells may then be transmitted into the digital network in an order consistent with the linked list pointers.

Claims

1. A method comprising:

generating a data frame having data information at a processor;

storing the data frame in a memory;

providing the data frame to a processor interface having a segmentation engine and a direct memory access (DMA) engine;

segmenting the data frame into a plurality of cells at the processor interface using the segmentation engine and the DMA engine; and

injecting each of said cells into a cell input engine by

transferring each of said cells to a number of memory locations by DMA transfer within a cell memory; and

establishing a series of linked list pointers associated with said memory locations, wherein said series of linked list pointers includes a logical queue;

wherein the number of memory locations is based on a length of the data frame.

2. A method as in claim 1 further comprising the step of transmitting said cells into a digital network in an order specified by said linked list pointers.

3. A digital switch comprising:

a queuing circuit having a number of connection queues and class of service queues and configured to store a plurality of ATM cells, said cells including payload information and header information within said connection queues and said class of service queues based upon said header information; and

a segmentation and reassembly (SAR) engine coupled to said queuing circuit and configured to extract cells from said queuing circuit that are bound for a local processor of said switch so as to preserve said payload information and to create and inject cells formed from data frames originated by said local processor into said queuing circuit;

wherein said segmentation and reassembly engine includes a direct memory access (DMA) engine having a DMA channel, and a segmentation engine to segment a frame into a plurality of cells by using the DMA channel of the DMA engine,

wherein the SAR engine is configured to input cells into the queuing circuit by transferring each of said cells to a number of memory locations by DMA transfer within a cell memory; and

establishing a series of linked list pointers associated with said memory locations, wherein said series of linked list pointers includes a logical queue.

4. A digital switch as in claim 3 wherein said segmentation and reassembly engine is further configured to strip off said header information from said cells after extracting said cells.

5. A digital switch as in claim 4 wherein said segmentation and reassembly engine is further configured to perform error detection operations for frames of data reconstructed from extracted cells using payload information therefrom.

6. A digital switch as in claim 5 wherein said segmentation and reassembly engine is further configured to compute a CRC-32 value for use in said error detection operations.

7. A digital switch as in claim 6 wherein said segmentation and reassembly engine is further configured to overwrite the CRC-32 value for said reconstructed frames of data with a pass/fail flag according to said error detection operations.