Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator

• US 6,201,829 B1
• Filed: 04/03/1998
• Issued: 03/13/2001
• Est. Priority Date: 04/03/1998
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Schneider, Thomas R.
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Phu, Phuong
• Application Number:
  US09/055,197
• Time in Patent Office: 1,075 Days
• Field of Search: 375/219, 375/224, 375/225, 375/221, 714/733, 714/738, 714/739, 708/250, 708/252
• US Class Current: 375/221
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

A pseudo-random built in self test pattern generator is constructed of eight sequential D-flip flops and configured to output 10-bit wide pattern data which conforms to the 8B/1OB transmission protocol. The first and fifth D-flip flops of the array have their outputs split, with one leg of the split directly defining a character bit and the other leg of the split defining an inverted character bit. The outputs of the first, second, seventh and eighth D-flip flops are directed to a four input EXOR gate whose output is connected to the D input of the first D-flip flop of the array. Configured as a recirculating feed back loop, the pattern generator defines a sequence of 10-bit patterns in which no more than five sequential 1s or five sequential 0s are generated either within a pattern or on pattern boundaries. The pattern generator provides 255 Fiber Channel-type transmission characters to a Fiber Channel-type transceiver circuit which serializes the characters into a 1.06 GHz serial datastream and then deserializes the datastream into 10-bit transmission characters. The received transmission characters are analyzed and if they match with patterns transmitted, the transceiver circuit is deemed to be correctly operating at a 1.06 GHz characteristic frequency.

Claims

1. A transceiver circuit of the type adapted to interface between highspeed serial data signals at a 1.06 GHz data rate, and 10-bit parallel encoded transmission character bytes, the transceiver circuit comprising:

a transmitter section for encoding a 10-bit parallel encoded transmission character byte to a serial datastream, the transmitter section having a 10-bit wide parallel input and a serial output;

a receiver section for converting a serial datastream into a 10-bit parallel encoded transmission character byte, the receiver section having a serial input and a 10-bit parallel output;

a multiplexer, connected to receive a 10-bit wide transmission character at a first input, the multiplexer connected to output 10-bit wide parallel data to the transmitter parallel input;

a pattern generator, configured to generate 10-bit wide parallel data patterns in accordance with an 8B/10B transmission protocol sequence, the pattern generator comprising a linear array of eight series-connected sequential D-flip flops, each flip flop including a Q output, wherein each Q output of the linear array of D-flip flops defines a particular bit of a 10-bit wide parallel data word, the Q outputs of the first and fifth D-flip flops defining 2-bits, respectively, of the 10-bit wide parallel data word the pattern generator providing said parallel data to a second input of the multiplexer, the multiplexer operatively responsive to a mode signal to select either 10-bit wide transmission character data or 10-bit wide data patterns for outputting to the transmitter parallel input; and

a signature analyzer connected in parallel fashion to the parallel data output of the receiver section,

wherein the transmitter section serial output is coupled in feed-back fashion to the receiver section serial input, the multiplexer selecting 10-bit wide data patterns from the pattern generator for outputting to the transmitter parallel input in response to the mode signal being in an asserted condition, the transmitter serializing and transmitting the data patterns to the receiver at a characteristic operation frequency, the receiver section receiving and deserializing said data patterns into 10-bit wide parallel data, the signature analyzer sampling the 10-bit wide data patterns and returning a positive match indication signal if the last received 10-bit wide data pattern matches the last transmitted 10-bit wide data pattern generated by the pattern generator.

2. The transceiver circuit according to claim 1, further comprising a reference clock signal having a fixed, uniform frequency, the reference clock signal continuously operative at said frequency, the transmitter section operatively responsive to said reference clock signal to serialize 10-bit wide parallel data into a 1.06 GHz serial datastream.

3. The transceiver circuit according to claim 2, the receiver section further comprising a receiver phase lock loop operatively responsive to the reference clock signal to thereby develop an output timing signal having a frequency an integral multiple of said reference clock signal frequency, the receiver phase lock loop operatively responsive to a phase edge of an incoming serial datastream the datastream having a characteristic frequency substantially equal to the frequency of the receiver phase lock loop timing signal, the receiver phase lock loop deserializing and byte synching the incoming serial datastream to thereby define 10-bit wide parallel data.

4. The transceiver circuit according to claim 3, the pattern generator further comprising:

an input connected to said reference clock signal; and

a linear feedback shift register, configured as a recirculating feedback loop.

5. The transceiver circuit according to claim 4, the linear feedback shift register comprising:

a linear array of 8, series-connected sequential D-flip flops, each D-flip flop having a D input, a reset input, a Q output and a clock input, each clock input connected and operatively responsive to said reference clock signal; and

a four input EXOR gate, the EXOR gate having an output coupled to the D input of the first sequential D-flip flop of the array, the inputs of the EXOR gate being taken from the Q outputs of the first, second, seventh and eighth D-flip flops of the of the array.

6. The transceiver circuit according to claim 5, wherein the 2-bits defined by the Q output of the first D-flip flop of the array have opposite logical states, and wherein the 2-bits defined by the Q output of the fifth D-flip flop of the array likewise have opposite logical states.

7. The transceiver circuit according to claim 6, wherein the Q-output of the first D-flip flop of the array directly defines the second bit of the 10-bit wide parallel data word, the first bit being defined by inverting the second bit.

8. The transceiver circuit according to claim 7, wherein the Q output of the fifth D-flip flop of the array directly defines the seventh bit of the 10-bit wide parallel data word, the sixth bit being defined by inverting the seventh bit.

9. The transceiver circuit according to claim 8, wherein the linear feedback shift register is initially reset and subsequently operatively responsive to the reference clock signal, the linear feedback shift register shifting data through the D-flip flops, the EXOR gate and inverter elements in combination conditioning the 10-bit parallel data output from the register, such that the 10-bit parallel data defines sequential patterns of 1s and 0s with no single pattern comprising more than five sequential 1s or five sequential 0s.

10. The transceiver circuit according to claim 9, wherein no more than five sequential 1s or five sequential 0s are generated within sequential patterns.

11. A pseudo-random built in self test pattern generator of the type adapted to provide 10-bit wide pattern data to a Fibre Channel-type transceiver circuit, the transceiver circuit operating at a characteristic frequency of about 1.06 GHz, the pattern generator comprising:

an input connected to a reference clock signal, the clock signal having a fixed, uniform frequency, the reference clock signal continuously operative at said frequency; and

a linear feedback shift register, configured as a recirculating feedback loop, the linear feedback shift register configured to generate 10-bit wide parallel data patterns in accordance with an 8B/10B transmission protocol sequence, the linear feedback shift register comprising a linear array of eight series-connected sequential D-flip flops, each flip flop including a Q output, wherein each Q output of the linear array of D-flip flops defines a particular bit of a 10-bit wide parallel data word, the Q outputs of the first and fifth D-flip flops defining 2-bits, respectively, of the 10-bit wide parallel data word.

12. The pattern generator according to claim 11, the linear feedback shift register comprising:

a linear array of 8, series-connected sequential D-flip flops, each D-flip flop having a D input, a reset input, a Q output and a clock input, each clock input connected and operatively responsive to said reference clock signal; and

a four input EXOR gate, the EXOR gate having an output coupled to the D input of the first sequential D-flip flop of the array, the inputs of the EXOR gate being taken from the Q outputs of the first, second, seventh and eighth D-flip flops of the of the array.

13. The pattern generator according to claim 12, wherein the 2-bits defined by the Q output of the first D-flip flop of the array have opposite logical states, and wherein the 2-bits defined by the Q output of the fifth D-flip flop of the array likewise have opposite logical states.

14. The pattern generator according to claim 13, wherein the Q-output of the first D-flip flop of the array directly defines the second bit of the 10-bit wide parallel data word, the first bit being defined by inverting the second bit.

15. The pattern generator according to claim 14, wherein the Q output of the fifth D-flip flop of the array directly defines the seventh bit of the 10-bit wide parallel data word, the sixth bit being defined by inverting the seventh bit.

16. The pattern generator according to claim 15, wherein the linear feedback shift register is initially reset and subsequently operatively responsive to the reference clock signal, the linear feedback shift register shifting data through the D-flip flops, the EXOR gate and inverter elements in combination conditioning the 10-bit parallel data output from the register, such that the 10-bit parallel data defines sequential patterns of 1s and 0s with no single pattern comprising more than five sequential 1s or five sequential 0s.

17. The pattern generator according to claim 16, wherein no more than five sequential 1s or five sequential 0s are generated within sequential patterns.