Processor having a clock driven CPU with static design

• US 6,202,104 B1
• Filed: 07/28/1998
• Issued: 03/13/2001
• Est. Priority Date: 07/28/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Ober, Robert Edmond
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/124,183
• Time in Patent Office: 959 Days
• Field of Search: 710/22, 710/260, 710/264, 710/266, 710/5, 710/18, 713/322, 713/323, 713/324, 713/320, 714/34
• US Class Current: 710/18
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A processor comprises a central processing unit being clock driven and having a static design. A memory is coupled with the central processing unit for storing interrupt routines and data. An interrupt control unit is coupled with said central processing unit for generating interrupt signals. An interrupt execution unit is provided for executing interrupt routines. If no interrupt routine is being executed the central processing unit is stopped from operating.

Claims

1. Processor comprising a central processing unit having a control output, being clock driven and having a static design, a controllable clock unit generating a processor clock fed to said central processing unit having a clock disable input coupled with said control output of said central processing unit, a memory coupled with said central processing unit for storing interrupt routines and data, an interrupt control unit coupled with said central processing unit for generating interrupt signals, an interrupt execution unit for executing interrupt routines, whereby if no interrupt routine is being executed said clock unit is disabled and the central processing unit is stopped from operating.

2. Processor according to claim 1 wherein said controllable clock unit comprises a clock enable input coupled with said interrupt control unit.

3. Processor according to claim 2, wherein said memory comprises two separate memory blocks, one for storing program code and one for storing data.

4. Processor according to claim 2, wherein said interrupt control unit comprises an interrupt arbitration unit for prioritizing interrupts.

5. Processor according to claim 4, wherein said interrupt unit generates an interrupt signal and an interrupt vector fed to said central processing unit.

6. Processor according to claim 2, wherein said processor provides direct memory access and comprises an exception unit generating an exception signal, whereby interrupt signals are associated to respective channels of a direct memory access.

7. Processor according to claim 6, wherein said exception unit generates an exception signal upon exceeding a programmable number of direct memory address channels.

8. Processor according to claim 6, wherein said exception unit generates an exception signal upon exceeding a programmable number of direct memory address channels executed in parallel.

9. Processor according to claim 2, wherein said central processing unit comprises an instruction execution count unit and an exception unit generating an exception signal upon exceeding a programmable number of instructions executed during one interrupt routine.

10. Processor according to claim 2, wherein said central processing unit comprises a mode control register associated to an interrupt routine which controls execution of said interrupt routine, whereby said mode control register defines whether said interrupt routine starts at a predetermined address or at a programmable address.

11. Processor according to claim 2, wherein said central processing unit comprises a programmable debug compare unit comprising a control register.

12. Processor according to claim 11, wherein said programmable debug compare unit disables said clock control unit upon a predefined condition.

13. Processor according to claim 11, wherein said programmable debug compare unit generates a debug signal.

14. Processor according to claim 11, wherein said programmable debug compare unit captures status information of said central processing unit.

15. Processor comprising a central processing unit being clock driven and at least one control output a memory coupled with said central processing unit for storing interrupt routines and data, an interrupt control unit couples with said central processing unit for generating interrupt signals, controllable clock unit generating at least a first and a second processor clock fed to said central processing unit, said first clock being higher than said second clock, whereby said controllable clock unit comprises a clock control input coupled with said interrupt control unit and with said control output of said central processing unit, whereby said clock unit generates said first clock if any interrupt routine is executed and said second clock if no interrupt routine is executed whereby if no interrupt routine is being executed the central processing unit is stopped from operating.

16. Processor according to claim 15, wherein said memory comprises two separate memory blocks, one for storing program code and one for storing data.

17. Processor according to claim 15, wherein said interrupt control unit comprises a interrupt arbitration unit for prioritizing interrupts.

18. Processor according to claim 17, wherein said interrupt unit generates an interrupt signal and an interrupt vector fed to said central processing unit.

19. Processor according to claim 15, wherein said processor provides direct memory access and comprises an exception unit generating an exception signal, whereby interrupt signals are associated to respective channels of a direct memory access.

20. Processor according to claim 19, wherein said exception unit comprises a comparator generating an exception signal upon exceeding a programmable number of direct memory address channels.

21. Processor according to claim 19, wherein said exception unit comprises a comparator generating an exception signal upon exceeding a programmable number of direct memory address channels being executed at the same time.

22. Processor according to claim 15, wherein said central processing unit comprises an instruction execution count unit and an exception unit generating an exception signal upon exceeding a programmable number of instructions executed during one interrupt routine.

23. Processor according to claim 15, wherein said central processing unit comprises a mode control register associated to an interrupt routine which controls execution of said interrupt routine, whereby said mode control register defines whether said interrupt routine starts at a predetermined address or at a programmable address.

24. Processor according to claim 15, wherein said central processing unit comprises a programmable debug compare unit comprising a control register.

25. Processor according to claim 24, wherein said programmable debug compare unit disables said clock control unit upon a predefined condition.

26. Processor according to claim 24, wherein said programmable debug compare unit generates a debug signal.

27. Processor according to claim 24, wherein said programmable debug compare unit captures status information of said central processing unit.