Fault tolerant redundant bus bridge systems and methods

• US 6,202,115 B1
• Filed: 04/17/1998
• Issued: 03/13/2001
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Khosrowpour, Farzad
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/062,279
• Time in Patent Office: 1,061 Days
• Field of Search: 710/100-131
• US Class Current: 710/312
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

First and second bus bridges, e.g., first and second RAID disk controllers, are operative to communicate between a first bus and a second bus via respective first and second caches and to transfer information from the first bus bridge to the second cache over a third bus, e.g., a synchronous data link between the caches, to allow recovery of data previously cached in the first cache via the second bus bridge. The second bus bridge preferably is operative to transfer information addressed to the first bus from the first bus to the second bus, e.g., to “alias” addresses normally assigned to the first bus bridge in event of a failure, disconnection or other change in status of the first bus bridge. The status may be communicated from the first bus bridge to the second bus bridge over a fourth bus connecting the first and second bus bridges. In one embodiment, the first and second bus bridges are included in respective first and second circuit assemblies that are connected to the first and second busses and to one another by a conductor assembly, e.g., a relatively high-reliability passive backplane. In yet another embodiment according to the present invention, a a respective one of the first and second circuit assemblies comprises a first circuit substrate configured to be releasably connected to the conductor assembly. The first circuit substrate is configured to receive a plurality of second circuit substrates for connecting the bus bridge of the circuit assembly to the first and second busses. In this manner, the circuit assemblies may be adapted to bridge a variety of bus types, such as low-voltage differential SCSI (LVDS), single-ended ended SCSI (SCSI-SE) and Fibre Channel (FC).

Claims

1. A fault-tolerant redundant bus bridge system for communicating between a first bus and a second bus, the system comprising:

a first bus bridge and a second bus bridge, each configured to connect between the first and second busses, said first and second bus bridges concurrently operative to communicate between the first and second busses via respective first and second caches included therein; and

a third bus connecting said first and second bus bridges,

wherein said first bus bridge, said second bus bridge and said third bus are operative to transfer information from said first bus bridge to said second cache.

2. A system according to claim 1, wherein said second bus bridge is operative to transfer information from said second cache to the second bus responsive to change in a status of said first bus bridge to thereby recover information cached in said first cache.

3. A system according to claim 1, wherein said second bus bridge is operative to transfer information addressed to said first bus bridge from the first bus to the second bus.

4. A system according to claim 3, wherein said second bus bridge is operative to transfer information addressed to said first bus bridge from the first bus to the second bus responsive to a change in a status of said first bus bridge.

5. A system according to claim 1, wherein said first and second bus bridges comprise respective first and second RAID controllers.

6. A system according to claim 1, wherein said first and second caches comprise respective first and second synchronous dynamic random access memories (SDRAMs), and wherein said first and second bus bridges are operative to synchronously transfer information to said second SDRAM over said third bus.

7. A system according to claim 1, wherein said first bus bridge, said second bus bridge and said third bus are operative to maintain communication between the first and second busses in the presence of a single fault in said first bus bridge and said second bus bridge.

8. A fault-tolerant redundant bus bridge system for communicating between a first bus and a second bus, the system comprising:

a conductor assembly;

a first circuit assembly connected to the first and second busses via said conductor assembly, said first circuit assembly including a first bus bridge operative to communicate between the first and second busses via a first cache included therein; and

a second circuit assembly connected to the first and second busses via said conductor assembly, said second circuit assembly including a second bus bridge operative to communicate between the first and second busses via a second cache included therein,

wherein said conductor assembly connects said first and second circuit bus bridges via a third bus such that said first bus bridge, said second bus bridge and said third bus are operative to transfer information from said first bus bridge to said second cache.

9. A system according to claim 8, wherein said conductor assembly comprises a backplane, and wherein said first and second circuit assemblies comprise respective first and second circuit substrates configured to releasably connect to said backplane.

10. A system according to claim 8, wherein said first and second bus bridges comprise respective first and second RAID controllers.

11. A system according to claim 8, wherein said second bus bridge is operative to transfer information from said second cache to the second bus responsive to a change in a status of said first b/us bridge to thereby recover information previously cached in said first cache.

12. A system according to claim 11, wherein said second circuit assembly is operative to monitor the status of said first circuit assembly over a fourth bus connecting said first and second circuit assemblies via said conductor assembly.

13. A system according to claim 8, wherein said second bus bridge is operative to transfer information addressed to said first bus bridge from the first bus to the second bus.

14. A system according to claim 8, wherein a respective one of said first and second circuit assemblies is operative to maintain communication between the first bus and the second bus during connection or disconnection of the other of said first and second circuit assemblies.

15. A system according to claim 8, further comprising a first power supply configured to be connected to said first circuit assembly via said conductor assembly to supply power to said first circuit assembly, and a second power supply configured to be connected to said second circuit assembly via said conductor assembly to supply power to said second circuit assembly.

16. A system according to claim 15, wherein said first and second circuit assemblies comprise first and second batteries which are operative to supply power to the first and second circuit assemblies, respectively, and wherein a respective one of said first and second circuit assemblies operate from the associated battery responsive to failure of the associated power supply.

17. A system according to claim 8, wherein said first cache comprises a first SDRAM, wherein said second cache comprises a second SDRAM.

18. A system according to claim 17, wherein said first and second circuit assemblies comprise respective first and second clock generators which produce respective first and second clock signals, and wherein said first and second circuit assemblies are operative to synchronously transfer information between said first circuit assembly and said second SDRAM in synchronism with a selected one of said first and second clock signals.

19. A system according to claim 18:

wherein said conductor assembly is configured to provide said first clock signal to said second circuit assembly;

wherein said second circuit assembly comprises;

a clock control circuit, responsive to said first clock signal, operative to determine a status of said first clock signal; and

a clock synchronizing circuit, responsive to said clock control circuit, operative to produce a clock signal synchronized to a selected one of said first and second clock signals based on the determined status of said first clock signal; and

wherein said first and second circuit assemblies are operative to transfer information from said first circuit assembly to said second SDRAM according to the synchronized clock signal.

20. A system according to claim 8, wherein a respective one of said first and second circuit assemblies comprises:

a first circuit substrate configured to be releasably connected to said conductor assembly, said first circuit substrate configured to receive a plurality of second circuit substrates for connecting said bus bridge of said circuit assembly to the first and second busses.

21. A system according to claim 8, wherein the first and second busses each comprise one of a Fibre Channel (FC) or a SCSI bus, and wherein a respective one of said first and second circuit assemblies are operative to communicate between the first and second busses via a PCI bus.

22. A circuit assembly for use in a fault-tolerant redundant bus bridge system that communicates between a first bus and a second bus through a conductor assembly, the assembly comprising:

a bus bridge configured to connect to the first and second busses through the conductor assembly and operative to communicate between the first and second busses via a cache included therein; and

a communications circuit operatively associated with said cache and operative to transfer information from said cache to a second bus bridge through said conductor assembly.

23. An assembly according to claim 22, wherein said communications circuit is operative to transfer information from the second bus bridge to said cache for subsequent transfer to the second bus.

24. An assembly according to claim 23, wherein said bus bridge is operative to transfer the information received from the second bus bridge in response to a change in a status of the second bus bridge.

25. An assembly according to claim 24, further comprising a status monitoring circuit responsive to the second bus bridge and operative to monitor a status thereof.

26. An assembly according to claim 22, wherein said bus bridge and said communications circuit are formed on a circuit substrate configured to releasably connect to said backplane.

27. An assembly according to claim 22, wherein said bus bridge comprises a RAID controller.

28. An assembly according to claim 22, wherein said bus bridge is operative to transfer information addressed to the second bus bridge from the first bus to the second bus.

29. An assembly according to claim 22, wherein said bus bridge is operative to maintain communication between the first bus and the second bus during connection or disconnection of the second bus bridge.

30. An assembly according to claim 22, wherein said bus bridge and second communications circuit are configured to receive power from an external supply to operate said bus bridge, and further comprising a battery operative to supply power to said bus bridge responsive to failure of the external power supply.

31. An assembly according to claim 22, wherein said cache comprises an SDRAM.

32. An assembly according to claim 31, comprising:

a clock generator operative to produce a local clock signal;

a clock control circuit responsive to an external clock signal and operative to determine a status of said external clock signal; and

a clock synchronizing circuit responsive to said clock control circuit and operative to produce a clock signal that is synchronized to a selected one of the external clock signal and the local clock signal based on the determined status of said external clock signal; and

wherein said bus bridge is operative to transfer information to said SDRAM according to the synchronized clock signal.

33. A system according to claim 22, wherein said bus bridge and second communications circuit are formed on a circuit substrate configured to receive a plurality of second circuit substrates for connecting said bus bridge to the first and second busses.

34. A fault-tolerant method of communicating between a first bus and a second bus, the method comprising the steps of:

connecting each of a first bus bridge and a second bus bridge between the first and second busses, said first and second bus bridges concurrently operative to communicate between the first and second busses via respective first and second caches included therein, said first and second bus bridges connected by a third bus independent of the first and second busses;

receiving information from the first bus at the first bus bridge;

caching the received information in the first cache;

transferring the received information from the first bus bridge to the second cache; and

transferring the information from the second cache to the second bus to recover information cached in the first cache.

35. A method according to claim 34, wherein said step of transferring information from the second cache to the second bus comprises the step of transferring information from the second cache to the second bus responsive to a change in a status of the first bus bridge.

36. A method according to claim 35, wherein said step of transferring information from the second cache to the second bus is preceded by the step of monitoring the status of the first bus bridge.

37. A method according to claim 36, further comprising the step of transferring information addressed to the first bus bridge from the first bus to the second bus via the second bus bridge.

38. A method according to claim 34, wherein the first and second bus bridges comprise respective first and second RAID controllers, and wherein said step of transferring information from the second cache to the second bus comprises the step of processing the transferred information according to a RAID level.

39. A method according to claim 34, wherein said step of transferring the received information to the second cache comprises the step of synchronously transferring the information from the first bus bridge to the second cache.

40. A method according to claim 34, comprising the step of maintaining communication between the first and second busses in the presence of a single fault in said first and second bus bridges.