Processor-cache protocol using simple commands to implement a range of cache configurations
First Claim
Patent Images
1. A system comprising:
- a processor having a cache control circuit, the cache control circuit to control multiple types of cache memories, the processor having a first level cache coupled with the cache control circuit;
a cache bus coupled to the processor; and
a second level cache coupled with the cache control circuit via the cache bus;
wherein the cache control circuit controls the first level cache and the second level cache by issuing one or more micro-operations from a set of micro-operations that are decoded and executed by the first level cache and the second level cache, respectively.
2 Assignments
0 Petitions
Accused Products
Abstract
A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.
125 Citations
36 Claims
-
1. A system comprising:
-
a processor having a cache control circuit, the cache control circuit to control multiple types of cache memories, the processor having a first level cache coupled with the cache control circuit;
a cache bus coupled to the processor; and
a second level cache coupled with the cache control circuit via the cache bus;
wherein the cache control circuit controls the first level cache and the second level cache by issuing one or more micro-operations from a set of micro-operations that are decoded and executed by the first level cache and the second level cache, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A processor comprising:
-
a first level cache memory; and
a cache control circuit to control multiple types of cache memory circuits, the cache control circuit having a first level cache interface coupled to the first level cache, wherein the cache control circuit communicates one or more micro-operations from a set of micro-operations that are decoded and executed by the first level cache, and a second level cache interface to communicate one or more micro-operations to a second level cache that decodes and executes the micro-operations, if the second level cache is communicatively coupled to the second level cache interface. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
-
25. A method comprising:
-
sending, selectively, a micro-operation from a set of micro-operations to control multiple types of cache memories, from a processor located on a first die to a cache memory circuit located on the first die or to a cache memory circuit located on a second die via a cache bus;
decoding the micro-operation by the cache memory receiving the micro-operation;
executing the micro-operation by the cache memory receiving the micro-operation; and
sending results, if indicated by the micro-operation, to the processor. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
-
Specification