Shared cache structure for temporal and non-temporal information using indicative bits

• US 6,202,129 B1
• Filed: 03/31/1998
• Issued: 03/13/2001
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Palanca, Salvador, Cooray, Niranjan L., Pentkovski, Vladimir, Tsai, Steve, Narang, Angad
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US09/053,386
• Time in Patent Office: 1,078 Days
• Field of Search: 711/136, 711/137, 711/145, 711/160, 711/125, 711/128, 711/129, 711/133, 711/159
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

Claims

1. A computer system having cache memory management, the computer system comprising:

a main memory;

a processor coupled to said main memory, said processor to execute instructions to process non-temporal data and temporal data;

at least one cache memory coupled to said processor, said at least one cache memory having at least two cache ways, each of said at least two cache ways comprising a plurality of sets of data stored in said at least one cache memory, each of said plurality of sets of data having a first bit and a second bit in said at least one cache memory, said first bit of each of said plurality of sets of data to indicate whether one of said at least two cache ways in the associated set of data contains said non-temporal data that can be replaced first, said non-temporal data being infrequently used by the processor, said second bit indicative of an order of data entry in a corresponding way; and

wherein said processor accesses data from one of said main memory or said at least one cache memory.

2. The computer system of claim 1, wherein the associated set of data does not contain said non-temporal data and said order is indicative of whether said data entry is a least recently used entry by the processor with respect to other data entries in the associated set of data.

3. The computer system of claim 1, wherein said first bit is set to indicate that one of said at least two cache ways in the associated set of data contains said non-temporal data which will be replaced upon a cache miss.

4. The computer system of claim 3, wherein the associated set of data contains said non-temporal data and said second bit points to said non-temporal data in one of said at least two cache ways in the associated set of data.

5. The computer system of claim 1, wherein said first bit is cleared to indicate that none of said at least two cache ways in the associated set of data contains said non-temporal data.

6. The computer system of claim 1, further comprising:

cache control logic coupled to said at least one cache memory and said processor, said cache control logic to control said at least one cache memory.

7. The computer system of claim 6, wherein said processor receives an instruction for accessing data, said processor determining if said data is located in said at least one cache memory, if so, accessing said data from said at least one cache memory, otherwise, accessing said data from said main memory.

8. The computer system of claim 7, wherein if said data is accessed from said at least one cache memory, said cache control logic determines if said data is temporal, and, if said data is temporal and if said first bit is not set to indicate non-temporal data then updating an order of said second bit corresponding to said way that is being accessed, otherwise leaving said order unchanged.

9. The computer system of claim 8, wherein said first bit associated with the set of data of said way being accessed is unchanged.

10. The computer system of claim 7, wherein if said data accessed from said at least one cache memory is non-temporal, said cache control logic configures said first bit to indicate that said accessed data is non-temporal, said cache control logic further updating said order of said second bit.

11. The computer system of claim 7, wherein if said data is accessed from said main memory, said cache control logic determines if said data is non-temporal, if so, configuring said first bit to indicate that said accessed data is non-temporal, said cache control logic leaving unchanged said order of said second bit.

12. The computer system of claim 11, wherein if said cache control logic determines that said data is temporal, said cache control logic configures said first bit to indicate that said accessed data is temporal, said cache control logic updating said order of said second bit.

13. The computer system of claim 1, wherein said first bit of each of said plurality of sets of data is a lock bit.

14. The computer system of claim 1, wherein said non-temporal data is a type of data that is predetermined to be infrequently used by the processor.

15. The computer system of claim 1, wherein said non-temporal data is a type of data that is streaming data that need not be cached.

16. A method in a computer system of allocating cache memory for replacement, the method comprising:

providing a main memory;

providing a processor coupled to said main memory, said processor to execute instructions to process non-temporal data and temporal data;

providing at least one cache memory coupled to said processor, said at least one cache memory having at least two cache ways, each of said at least two cache ways comprising a plurality of sets of data stored in said at least one cache memory, each of said plurality of sets of data having a first bit and a second bit in said at least one cache memory, said first bit of each of said plurality of sets of data to indicate whether one of said at least two cache ways in the associated set of data contains said non-temporal data that can be replaced first, said non-temporal data being infrequently used by the processor, said second bit indicative of an order of data entry in a corresponding way; and

accessing, by said processor, data from one of said main memory or said at least one cache memory.

17. The method of claim 16, wherein the associated set of data does not contain said non-temporal data and said order is indicative of whether said data entry is a least recently used entry by the processor with respect to other data entries in the associated set of data.

18. The method of claim 16, wherein said first bit is set to indicate that one of said at least two cache ways in the associated set of data contains said non-temporal data which will be replaced upon a cache miss.

19. The method of claim 18, wherein the associated set of data contains said non-temporal data and said second bit points to said non-temporal data in one of said at least two cache ways in the associated set of data.

20. The method of claim 16, wherein said first bit is cleared to indicate that none of said at least two cache ways in the associated set of data contains said non-temporal data.

21. The method of claim 16, further comprising:

providing a cache control logic coupled to said at least one cache memory and said processor, said cache control logic controlling said at least one cache memory.

22. The method of claim 21, wherein said processor receives an instruction for accessing data, said processor determining if said data is located in said at least one cache memory, if so, accessing said data from said at least one cache memory, otherwise, accessing said data from said main memory.

23. The method of claim 22, wherein if said data is accessed from said at least one cache memory, said cache control logic determines if said data is temporal, and, if said data is temporal and if said first bit is not set to indicate non-temporal data then updating an order of said second bit corresponding to said way that is being accessed, otherwise leaving said order unchanged.

24. The method of claim 22, wherein said first bit associated with the set of data of said way being accessed is unchanged.

25. The method of claim 22, wherein if said data accessed from said at least one cache memory is non-temporal, said cache control logic configures said first bit to indicate that said accessed data is non-temporal, said cache control logic further updating said order of said second bit.

26. The method of claim 22, wherein if said data is accessed from said main memory, said cache control logic determines if said data is non-temporal, if so, configuring said first bit to indicate that said accessed data is non-temporal, said cache control logic leaving unchanged said order of said second bit.

27. The method of claim 26, wherein if said cache control logic determines that said data is temporal, said cache control logic configures said first bit to indicate that said accessed data is temporal, said cache control logic updating said order of said second bit.

28. The method of claim 16, wherein said first bit of each of said plurality of sets of data is a lock bit.

29. The method of claim 16, wherein said non-temporal data is a type of data that is predetermined to be infrequently used by the processor.

30. The method of claim 16, wherein said non-temporal data is a type of data that is streaming data that need not be cached.

31. A data cache memory for storing temporal and non-temporal data therein, the data cache memory comprising:

one or more cache sets of data, each of the one or more cache sets of data comprising

at least two ways, each of the at least two ways to store data for the associated cache set of data;

one or more least recently used bits, the least recently used bits in one case to indicate the least recently accessed way of the associated cache set of data by a processor; and

a lock bit, the lock bit to indicate whether any one of the at least two ways within the associated cache set of data contains the non-temporal data that can be replaced first.

32. The data cache memory of claim 31, wherein the non-temporal data is a type of data that is predetermined to be infrequently used by the processor.

33. The data cache memory of claim 31, wherein the non-temporal data is a type of data that is streaming data that need not be cached.

34. The data cache memory of claim 31, wherein the lock bit is set for one cache set of data of the one or more cache sets of data and,

the lock bit indicating that the one cache set of data contains the non-temporal data

and

the one or more least recently used bits are updated to indicate which way of the at least two ways contains the non-temporal data.

35. A method for a data cache memory storing temporal and non-temporal data of indicating a non-temporal data entry that can be replaced with other data, the method comprising:

providing a cache memory having,

one or more sets of data, each of the one or more sets of data comprising

at least two ways, each of the at least two ways to store data for the associated set of data,

one or more least recently used bits, the least recently used bits in one case to indicate the least recently accessed way of the associated set of data by a processor, and

a lock bit, the lock bit to indicate whether any one of the at least two ways within the associated set of data contains the non-temporal data that can be replaced first;

determining whether data is temporal or non-temporal from a locality hint associated with an instruction processing the data; and

setting the lock bit for an associated set of data in the case that data stored into a way of the associated set of data is the non-temporal data.

36. The method of claim 35, wherein the non-temporal data is a type of data that is predetermined to be infrequently used.

37. The method of claim 35, wherein the non-temporal data is a type of data that is streaming data that need not be cached.

38. The method of claim 35, further comprising:

updating the one or more least recently used bits to indicate which way of the at least two ways contains the non-temporal data.

39. The method of claim 35, further comprising:

clearing the lock bit for an associated set of data in the case that data stored into a way of the associated set upon a cache miss is temporal.

40. The method of claim 35, wherein the instruction processing the data with the locality hint is a non-temporal instruction.

41. A method of clearing non-temporal data pollution in a data cache memory storing temporal and non-temporal data, the method comprising:

dynamically setting a first bit in a cache set of data in the data cache memory in response to a cache miss to the cache set during execution of a non-temporal instruction, the first bit indicating one of at least two ways within the cache set of data contains the non-temporal data, a second bit in the cache set of data indicating an order of data entry in the at least two ways within the cache set of data;

replacing the non-temporal data in one of the at least two ways with the temporal data in response to the first bit being set and a cache miss to the cache set during execution of a temporal instruction; and

dynamically clearing the first bit in the cache set of data in response to replacing the non-temporal data in the one of the at least two ways with the temporal data.

42. The method of claim 41, wherein the non-temporal data is a type of data that is predetermined to be infrequently used.

43. The method of claim 41, wherein the non-temporal data is a type of data that is streaming data that need not be cached.

44. The method of claim 41, wherein,

the data cache memory includes a plurality of cache sets of data and the dynamically setting of the first bit, the dynamically clearing of the first bit and the replacing non temporal data is performed one cache set at a time during instruction access to each cache set of the plurality of cache sets of data within the data cache memory.

45. The method of claim 41, further comprising:

updating the second bit of the cache set of data to point to which way of the at least two ways contains the non-temporal data in response to the cache miss to the cache set during execution of the non-temporal instruction.

46. The method of claim 45, further comprising:

maintaining the setting of the first bit and maintaining the second bit to point to which way of the at least two ways contains the non-temporal data in response to the cache hit to the cache set during execution of the temporal instruction.

47. The method of claim 45, further comprising:

maintaining the first bit set, and the second bit is not updated so as to remain pointing to which way of the at least two ways contains the non-temporal data in response to a cache hit to the cache set during execution of the non-temporal instruction and a mode bit being cleared.

48. The method of claim 45, further comprising:

setting the first bit in response to a cache hit to the cache set during execution of the non-temporal instruction and a mode bit being set.

49. The method of claim 48, further comprising:

updating the second bit of the cache set of data to point to which way of the at least two ways was hit in response to the cache hit to the cache set during execution of the non-temporal instruction and the mode bit being set.

50. The method of claim 41, further comprising:

maintaining the setting of the first bit in the cache set of data in response to a cache hit to the cache set during execution of the temporal instruction.

51. The method of claim 41, wherein,

the first bit is a lock bit.