Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

• US 6,202,138 B1
• Filed: 01/20/2000
• Issued: 03/13/2001
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US09/487,865
• Time in Patent Office: 418 Days
• Field of Search: 711/202, 711/102, 711/103, 711/104, 711/115, 711/5, 711/168, 364/200, 360/49, 360/39, 360/54, 360/31, 365/185.11, 365/200, 365/210, 365/230.03, 365/189.04
• US Class Current: 711/168
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a nonvolatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Claims

1. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each said sector including a user data portion and an overhead portion, said sectors being organized into blocks, each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA), said host-provided LBA being received by said storage device from the host for identifying a sector of information to be accessed, said actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored, said storage system comprising:

a memory controller coupled to said host; and

a nonvolatile memory bank coupled to said memory controller via a memory bus, said memory bank being included in a non-volatile semiconductor memory unit, said memory bank having storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in said memory unit, each said memory row-portions providing storage space for two of said sectors,

wherein the speed of performing write operations is increased by writing a plurality of sector information to the memory device simultaneously.

2. A memory storage system as recited in claim 1 wherein said memory controller includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating said LBA to said PBA; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

3. A memory storage system as recited in claim 1 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of an even sector, and

a first odd sector field for storing even data bytes of an odd sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said even sector, and

a second odd sector field for storing odd data bytes of said odd sector;

said memory bus includes,

a first split bus coupled to transmit said even data bytes of said sectors between said memory controller and said memory unit;

a second split bus coupled to transmit said odd data bytes of said sectors between said memory controller and said memory unit.

4. A memory storage system as recited in claim 3 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector;

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

5. A memory storage system as recited in claim 4 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector; and

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

6. A memory storage system as recited in claim 5 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

7. A memory storage system as recited in claim 6 wherein said controller includes:

means for accessing an even sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing an odd sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said memory units via said first and second split buses.

8. A memory storage system as recited in claim 7 wherein said controller includes error correction code logic for performing error coding and correction operations on said sector-organized information.

9. A memory storage system as recited in claim 8 wherein said flag field is used to store block level flags including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

10. A memory storage system as recited in claim 9 wherein each of said corresponding sub-blocks are identified by a single PBA value.

11. A memory storage system as recited in claim 10 wherein said non-volatile memory unit is a flash memory chip.

12. A memory storage system as recited in claim 11 wherein:

each of said first row-portions includes a first sector field for storing data bytes of a first sector;

each of said second row-portions includes a second sector field for storing data bytes of a second sector;

said memory bus includes,

a first split bus coupled to transmit the least significant data bytes of said sectors between said memory controller and said memory unit;

a second split bus coupled to transmit the most significant data bytes of said sectors between said memory controller and said memory unit.

13. In a storage system including a nonvolatile memory bank and a controller coupled to said memory bank via a memory bus, said memory bank being included in a non-volatile memory unit, said memory bank having blocks for storing sectors of information each of which includes a user data portion and an overhead portion, each said block having associated therewith a logical block address (LBA) and a physical block address (PBA), said LBA provided by a host to said controller for identifying a sector of information to be accessed, said PBA developed by said storage device for identifying a free block location within said memory bank wherein said accessed block is to be stored, each block including at least one memory row location having a first row-portion located in said memory unit, and a corresponding second row-portion located in said memory unit, said controller including a data buffer;

a process of writing sector-organized information to said memory bank, said process including the steps of;

receiving host-provided LBA values from said host, each said host-provided LBA value for identifying a sector of information;

modifying a current host-provided LBA to identify a block of sectors of information;

providing a map having map row locations identified by said modified LBA values or virtual PBA values, said map used as a look-up-table for storing virtual PBA values corresponding to modified LBA values;

setting a sector count value equal to the number of sectors of information identified by the host;

searching for a free block within said memory bank identified by a current virtual PBA;

storing said current virtual PBA, corresponding to said free block, in a map row location identified by said modified current LBA in said map;

determining whether said current host-provided LBA is even and whether said sector count is greater than one;

if said current actual PBA value is even and said sector count is greater than one,

simultaneously writing two sectors of information, one sector identified by said current host-provided LBA and a second sector of information identified by said current host-provided LBA plus one, said first sector being written to said memory unit and said second sector being written to said memory,

decrementing said sector count by two,

determining whether said sector count is equal to zero,

if said sector count is not equal to zero, increasing said current host-provided LBA value by two to point to the next sector that is to be written,

if said current host-provided LBA value or said sector count is not greater than one,

simultaneously writing even data bytes of a current sector of information identified by said current host-provided LBA to said memory unit and odd data bytes of said current sector to said memory unit,

decrementing said sector count by one,

determining whether said sector count is equal to zero, and

if said sector count is not equal to zero, increasing said current host-provided LBA by one to point to the next sector of information that is to be written.

14. In a storage system including a memory bank and a controller as recited in claim 13, wherein said step of simultaneously writing said two current sectors to said memory units of said memory bank, includes the steps of:

simultaneously providing a write command to said memory unit;

addressing one of said memory row locations of said memory bank by simultaneously addressing corresponding first and second row portions of said addressed row location;

storing even data bytes of an even sector to a first even sector field of said first addressed row-portion;

storing even data bytes of an odd sector to a first odd sector field of said first addressed row-portion;

storing odd data bytes of said even sector to a second even sector field of said second addressed row-portion; and

storing odd data bytes of said odd sector of information to a second odd sector field of said second addressed row-portion.

15. In a storage system including a memory bank and a controller as recited in claim 14, further including the steps of:

determining whether or not each of said addressed sector locations of a current block has been accessed since the last erasure thereof;

setting a move flag corresponding to said current block if said current block has been accessed since the last erasure thereof;

subsequent to performing a write operation

determining whether said move flag is set;

if said move flag is set, updating said current block by moving those of said sectors not written to which belong to said current block to corresponding sector locations in said free block.

16. A memory storage system comprising:

memory control circuitry coupled to a host for transferring therebetween sectors of information; and

a nonvolatile memory unit for storing information organized into sectors, said nonvolatile memory unit coupled to said memory control circuitry via a memory bus for receiving more than one sector of information from the host, said memory unit having blocks each of which includes a plurality rows, each row including a plurality of row-portions, each said memory row-portions providing storage space for at least one of said sectors,

wherein the speed of performing write operations is increased by writing two or more sectors of information to a row of the nonvolatile memory unit simultaneously.

17. A memory storage system as recited in claim 16 wherein said nonvolatile memory unit includes one or more nonvolatile memory devices and wherein said rows of a block span across one or more nonvolatile memory devices.

18. A memory storage system as recited in claim 17 wherein said row-portions including a user data portion and an overhead portion.

19. A memory storage system as recited in claim 18 wherein said row of a block includes a first row-portion, and a second row-portion.

20. A memory storage system as recited in claim 19 wherein said memory control circuitry is coupled to a host for communicating command, address and data information therebetween.

21. A memory storage system as recited in claim 16 wherein said memory control circuitry includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating logical block addresses to physical block addresses; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

22. A memory storage system as recited in claim 19 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of a first sector, and

a first odd sector field for storing even data bytes of a second sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said first sector, and

a second odd sector field for storing odd data bytes of said second sector;

said memory bus includes,

a first split bus coupled to transfer said even data bytes of said sectors between said memory control circuitry and said memory unit;

a second split bus coupled to transfer said odd data bytes of said sectors between said memory control circuitry and said memory unit.

23. A memory storage system as recited in claim 22 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector;

a block address field for storing a physical block address for identifying an address of said corresponding block; and

a flag field for storing information indicative of the status of said corresponding block.

24. A memory storage system as recited in claim 23 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector; and

a block address field for storing said physical block address identifying an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

25. A memory storage system as recited in claim 24 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

26. A memory storage system as recited in claim 24 wherein said memory control circuitry includes:

means for accessing a first sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing a second sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said memory units via said first and second split buses.

27. A memory storage system as recited in claim 26 wherein said memory control circuitry includes error correction code logic for performing error coding and correction operations on said sector-organized information.

28. A memory storage system as recited in claim 27 wherein said flag field including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

29. A memory storage system as recited in claim 28 wherein said nonvolatile memory unit includes one or more flash memory chips.

30. A memory storage system as recited in claim 19 wherein:

said memory bus includes,

a first split bus coupled to transfer the least significant data bytes between said memory control circuitry and said memory unit; and

a second split bus coupled to transfer the most significant data bytes between said memory control circuitry and said memory unit.

31. A memory storage system comprising:

memory control circuitry; and

a nonvolatile memory unit for storing information organized into sectors, said nonvolatile memory unit coupled to said memory control circuitry via a memory bus, said memory unit having blocks each of which includes a plurality rows, each row including a plurality of row-portions, each said memory row-portions providing storage space for at least one of said sectors,

wherein the speed of performing write operations is increased by writing two or more sectors of information to a row of the nonvolatile memory unit simultaneously.

32. A memory storage system as recited in claim 31 wherein said nonvolatile memory unit includes one or more nonvolatile memory devices and wherein said rows of a block span across one or more nonvolatile memory devices.

33. A memory storage system as recited in claim 32 wherein said row-portions including a user data portion and an overhead portion.

34. A memory storage system as recited in claim 33 wherein said row of a block include a first row-portion, and a second row-portion.

35. A memory storage system as recited in claim 34 wherein said memory control circuitry is coupled to a host for communicating command, address and data information therebetween.

36. A memory storage system as recited in claim 31 wherein said memory control circuitry includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating logical block addresses to physical block addresses; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

37. A memory storage system as recited in claim 34 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of a first sector, and

a first odd sector field for storing even data bytes of a second sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said first sector, and

a second odd sector field for storing odd data bytes of said second sector;

said memory bus includes,

a first split bus coupled to transfer said even data bytes of said sectors between said memory control circuitry and said memory unit;

a second split bus coupled to transfer said odd data bytes of said sectors between said memory control circuitry and said memory unit.

38. A memory storage system as recited in claim 37 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector;

a block address field for storing a physical block address for identifying an address of said corresponding block; and

a flag field for storing information indicative of the status of said corresponding block.

39. A memory storage system as recited in claim 38 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector; and

a block address field for storing said physical block address identifying an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

40. A memory storage system as recited in claim 39 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

41. A memory storage system as recited in claim 39 wherein said memory control circuitry includes:

means for accessing a first sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing a second sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said memory units via said first and second split buses.

42. A memory storage system as recited in claim 41 wherein said memory control circuitry includes error correction code logic for performing error coding and correction operations on said sector-organized information.

43. A memory storage system as recited in claim 42 wherein said flag field including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

44. A memory storage system as recited in claim 43 wherein said nonvolatile memory unit includes one or more flash memory chips.

45. A memory storage system as recited in claim 34 wherein:

said memory bus includes,

a first split bus coupled to transfer the least significant data bytes between said memory control circuitry and said memory unit;

a second split bus coupled to transfer the most significant data bytes between said memory control circuitry and said memory unit.

46. In a storage system including a nonvolatile memory unit and a controller coupled to said memory unit, a method of performing memory management comprising:

partitioning the memory unit into plurality of blocks, each of which includes a plurality of rows for storing sectors, and further partitioning a row into a plurality of row-portions, each of said memory row-portions providing storage space for storing at least one of said sectors,

wherein the speed of performing write operations is increased by writing two or more sector information to a row of the nonvolatile memory unit simultaneously.

47. In a storage system as recited in claim 46, the method further comprising defining a first row-portion and a second row-portion within a row of a block, providing a first sector having a first data byte and a second data byte and providing a second sector having a first data byte and a second data byte.

48. In a storage system as recited in claim 47, the method further comprising:

addressing one of said memory rows by simultaneously addressing corresponding first and second row-portions of said addressed row;

transferring the first data byte of said first sector to said memory unit while simultaneously transferring the second data byte of said first sector to said memory unit and after transferring all of the bytes of the first sector, transferring the first byte of said second sector to said memory unit while simultaneously transferring the second byte of said second sector to said memory unit,

wherein two sectors of information are stored in one memory row by simultaneously transferring two bytes of sector, said first byte being an even data byte of one of said first and second sectors and said second data byte being an odd data byte of one of said first and second sectors.

49. In a storage system as recited in claim 48 wherein even user data bytes of said first and second sectors are stored in said first memory row-portion and odd user data bytes of said first and second sectors are stored in said second memory row-portion and wherein overhead information associated with said first and second sectors is stored in one of said first and second row-portions.

50. In a storage system as recited in claim 49, the method further comprising entering a block address entry in a block address field in a last row of each said block.

51. A method of managing information stored within a nonvolatile memory unit, the memory unit including blocks for storing sectors of information, each block including at least one memory row having a first row-portion and a corresponding second row-portion, the method including the steps of:

setting a sector count value equal to the number of sectors of information to be written;

determining whether said sector count is greater than one;

if said sector count is greater than one, simultaneously writing a first sector and a second sector of information;

decrementing said sector count by two;

if said sector count is not equal to zero, pointing to the next sector that is to be written;

if said sector count is not greater than one, simultaneously writing even data bytes of a current sector of information to said memory unit and odd data bytes of said current sector to said memory unit;

decrementing said sector count by one; and

if said sector count is not equal to zero, pointing to the next sector of information that is to be written.

52. A method of managing information as recited in claim 51, wherein said step of simultaneously writing said two current sectors to said memory unit includes the steps of:

simultaneously providing a write command to said memory unit;

addressing one of said memory rows of said memory unit by simultaneously addressing corresponding first and second row portions of said addressed row;

storing even data bytes of a first sector to a first even sector field of said first addressed row-portion;

storing even data bytes of a second sector to a first odd sector field of said first addressed row-portion;

storing odd data bytes of said first sector to a second even sector field of said second addressed row-portion; and

storing odd data bytes of said second sector of information to a second odd sector field of said second addressed row-portion.

53. A method of managing information as recited in claim 52, further including the steps of:

determining whether or not each of said addressed rows of a current block has been accessed since the last erasure thereof;

finding a free block; and

updating said current block by moving those of said sectors not written which belong to said current block to corresponding sector locations in said free block.

54. A method of managing information as recited in claim 53, further including the steps of:

setting a move flag corresponding to said current block if said current block has been accessed since the last erasure thereof; and

subsequent to performing a write operation to the free flag, determining whether said move flag is set; and

performing said updating step if said move flag is set.