Programmable digital signal processor integrated circuit device and method for designing custom circuits from same

• US 6,202,197 B1
• Filed: 04/10/1990
• Issued: 03/13/2001
• Est. Priority Date: 07/11/1988
• Status: Expired due to Term

• Current Assignee: Logic Devices Incorporated
• Original Assignee: Logic Devices Incorporated
• Inventors: Robinson, Jeffrey I., Rouse, Keith
• Primary Examiner(s): Treat, William M.
• Application Number:
  US07/474,742
• Time in Patent Office: 3,990 Days
• Field of Search: 395/500, 395/200, 395/800, 703/13, 703/14, 703/15, 703/16, 716/4, 716/16, 716/17, 716/18, 712/36, 712/43, 712/35
• US Class Current: 712/36
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 15/7835 on more than one IC chip
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40). Parameters and microinstructions for the programmable signal processors (300) are sent via the communications bus (40), the core (30), and the parametric/microinstruction (35) bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports (62,66,68) and via the D/A and A/D (54,52) converters of the apparatus. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the apparatus.

Claims

1. A programmable apparatus for interfacing with a communications bus, said apparatus comprising:

a) a plurality of programmable signal processor means having means for receiving and storing parameters and microinstructions, and means for executing microinstructions, each said programmable signal processor means for performing an operation according to said microinstructions and said parameters on signal data received by said programmable signal processor means;

b) a core means comprising interface means for interfacing with said communications bus, decoder means for distinguishing between at least topological and parametric data received by said core means over said communications bus, and matrix switching means for interconnecting at least two of said plurality of programmable signal processor means in a desired manner in response to said topological data received over said communications bus;

c) a plurality of data bus means for connecting said plurality of programmable signal processor means to said matrix switching means; and

d) at least one third bus means coupled to said core means and to said means for receiving and storing, for transmitting said parametric data and said microinstructions to said means for receiving and storing of at least a plurality of said programmable signal processor means.

2. A programmable apparatus according to claim 1, further comprising:

e) a first non-volatile programmable memory means, for storing topological, parametric and microinstruction data for said programmable apparatus.

3. A programmable apparatus according to claim 1, wherein:

said plurality of programmable signal processors include means for providing control outputs indicative of the state of said the respective programmable signal processors; and

said interface means of said core means constitutes an intelligent buffer means for receiving at least said parametric data and addresses associated with said parametric data, and for receiving said control outputs indicative of the states of the respective programmable signal processors, said intelligent buffer means forwarding said parametric data via said third bus means to appropriate means for receiving and storing parameters of said programmable signal processors when permitted by said control outputs.

4. A programmable apparatus according to claim 3, further comprising:

an analog to digital converter, a digital to analog converter, a serial input port, and serial output port, each of which is coupled to said core means.

5. A programmable apparatus according to claim 4, wherein:

said processing means of said core means distinguishes between at least topological data, parametric data, and signal data.

6. A programmable apparatus according to claim 5, wherein:

said core means further comprises a plurality of parallel register means for interfacing said communications bus and said plurality of programmable signal processors, and for permitting signal data to be written directly to or read directly from said programmable signal processors via said communications bus and an associated said parallel register means.

13. A programmable apparatus according to claim 3, further comprising:

f) topology and parameter determination means for determining in conjunction with a computer, a suitable topology for said programmable apparatus, and suitable parameters for said programmable signal processing means in response to input into said computer by a user of desired programmable system functioning, wherein said topology and parameter determination means is coupled to said communications bus, and said suitable topology and parameters are translated by said topology and parameter determination means into topological and parametric data, said parametric data being forwarded to said first programmable memory means via said communications bus, and said parametric data being forwarded to each of said means for receiving and storing parameters via said communications bus, said core means, and said at least one third bus.

7. A programmable system, comprising:

a) a communications bus;

b) a plurality of programmable apparatus which interface with said communications bus, each said apparatus comprising,

1) a plurality of programmable signal processor means having means for receiving and storing parameters and microinstructions, and means for executing microinstructions, each said programmable signal processor means for performing an operation according to said microinstructions and said parameters on signal data received by said programmable signal processor means;

2) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, and matrix switching means for interconnecting at least two of said plurality of programmable signal processor means in a desired manner in response to said topological data received over said communications bus; and

3) a plurality of data bus means for connecting said plurality of programmable signal processor means to said matrix switching means; and

4) at least one third bus means coupled to said core means and to said means for receiving and storing for transmitting said parametric data and said microinstructions to said means for receiving and storing of a plurality of said programmable signal processor means;

c) linkage means coupled to said at least two of said plurality of programmable apparatus, for carrying signal data and timing signals between the same.

8. A programmable system according to claim 7, wherein:

said core means of each said plurality of programmable apparatus further comprises test function means for testing at least one of said programmable signal processor means to determine whether said at least one of said programmable signal processor means is functioning properly.

9. A programmable system according to claim 7, wherein:

each of said programmable apparatus further comprises a first non-volatile programmable memory means coupled to said communications bus for storing topological, parametric, and microinstruction data for said programmable apparatus.

10. A programmable system according to claim 7, wherein:

said plurality of programmable signal processors include means for providing control outputs indicative of the state of said the respective programmable signal processors; and

said interface means of said core means constitutes an intelligent buffer means for receiving at least said parametric data and addresses associated with said parametric data, and for receiving said control outputs indicative of the states of the respective programmable signal processors, said intelligent buffer means forwarding said parametric data via said third bus means to appropriate means for receiving and storing parameters of said programmable signal processors when permitted by said control outputs.

11. A programmable system according to claim 10, wherein:

each of said core means further comprises a plurality of parallel register means for interfacing said communications bus with at least a plurality of said programmable signal processors, and for permitting signal data to be written directly to or read directly from said a programmable signal processor via said communications bus and an associated said parallel register means.

12. A programmable system according to claim 10, in conjunction with topology and parameter determination means for determining for each of said plurality of programmable apparatus, in conjunction with a computer, a suitable topology for each of said programmable apparatus, and suitable parameters and microcode for each said programmable signal processor means in response to input into said computer by a user of desired programmable system functioning, wherein said topology and parameter determination means is coupled to said communications bus, and said suitable topology and parameters are translated by said topology and parameter determination means into topological and parametric data, said parametric data being forwarded to said first programmable memory means of each said plurality of programmable apparatus via said communications bus, said intelligent buffer means of said core means of each respective programmable apparatus, and said at least one third bus of each respective programmable apparatus.

14. A method for designing a custom programmable apparatus, said apparatus interfacing with a communications bus and having a plurality of programmable signal processor means which are programmed with parameters and microinstructions for controlling and performing operations on received signal data, a core means capable of interfacing with said communications bus, of distinguishing between at least topological, signal, and at least one of parametric and microinstruction data received by said core means over said communications bus, and of interconnecting at least two of said plurality of programmable signal processor means via a plurality of signal data bus means in a desired manner, and at least one third bus means for carrying parametric information and microinstruction information from said core means to said programmable signal processor means, said method comprising:

a) determining suitable interconnections of said plurality of said programmable signal processor means and said signal data bus means for accomplishing desired functions on data flowing therethrough;

b) determining suitable parameters and microinstructions for said programmable signal processor means;

c) arranging said core means by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections; and

d) providing said determined suitable parameters and microinstructions for said programmable signal processor means to said programmable signal processor means by coding said suitable parameters into second code and forwarding said second code via said communications bus, said core means, and said at least one said third bus means to a desired programmable signal processor means.

15. A method according to claim 14, wherein:

said steps of determining suitable interconnections and suitable parameters and microinstructions comprise inputting into a processor controlling said communications bus indications of a desired transfer function for said apparatus, wherein said processor is programmed to obtain said desired transfer function and to synthesize therefrom said suitable interconnections and said suitable parameters and microinstructions.

16. A method for designing a custom apparatus having a plurality of functional block means having desired parameters for performing desired operations on received signal data, and means for interconnecting in a desired manner at least two of said plurality of functional block means, said method comprising:

a) obtaining a programmable apparatus which interfaces with a communications bus, said apparatus having a plurality of programmable signal processor means for performing operations on received signal data, a core means capable of interfacing with said communications bus and of interconnecting at least two of said plurality of programmable signal processor means in a desired manner, a plurality of signal data bus means for carrying said signal data, and at least one third bus means for obtaining and carrying parametric data and microinstruction data to said programmable signal processor means;

b) in conjunction with a processor coupled to at least said communications bus, determining suitable interconnections of said plurality of programmable signal processors of said programmable apparatus, and determining suitable parameters and microinstructions for said programmable signal processor means of said programmable apparatus;

c) arranging said core means of said programmable apparatus by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;

d) providing said determined suitable parameters and suitable microinstructions to said programmable signal processor means of said programmable apparatus by coding said suitable parameters and microinstructions into second code and forwarding said second code via said at least one third bus to a desired programmable signal processor means of said programmable apparatus;

e) testing said programmable apparatus to determine whether said programmable apparatus is suitable for performing said desired operations;

f) finalizing core interconnection design, and finalizing said parameter values and microinstructions for said programmable signal processor means; and

g) producing integrated circuits based on said finalized interconnection design and based on said parameter values and microinstructions, said integrated circuits having at least a plurality of functional block means functionally equivalent to those programmable signal processor means utilized in said finalizing step, said functional block means having said finalized parameter values.

17. A programmable apparatus comprising:

a) a communications bus for transmitting signal data, parameters, and microinstructions from a host;

b) at least one programmable signal processor means having means for receiving and storing said parameters and microinstructions, means for executing microinstructions, and control output means for outputting signals indicating the state of said programmable signal processor means, said programmable signal processor means for performing an operation according to said microinstructions and said parameters on said signal data received by said programmable signal processor means;

c) a core means comprising processing means for distinguishing between at least signal and parametric data received by said core means over said communications bus, intelligent buffer means for interfacing with said communications bus, for receiving said parametric data, for receiving said signals from said control output means, and for outputting said parametric data in response to said signals from said control output means;

d) at least one data bus means for coupling said communications bus to said programmable signal processor means via said core means and transmitt ing signal data thereover; and

e) at least one third bus means coupling said intelligent buffer means to said means for receiving and storing parameters and microinstructions, for transmitting said parameters and microinstructions thereover.

18. A programmable apparatus according to claim 17, wherein said host constitutes a non-volatile programmable memory means.

19. A programmable apparatus for interfacing with a communications bus, said apparatus comprising:

a) a plurality of functional block means, each said functional block means for performing an operation on signal data received by said functional block means;

b) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, matrix switching means for interconnecting at least two of said plurality of functional block means in a desired manner in response to said topological data received over said communications bus, wherein parametric data received by said processing means is sent by said processing means via a parametric bus to at least a first of said functional block means to control internal parameters of a least said first of said functional block means, and wherein signal data is received by said plurality of functional block means via data busses coupled to said matrix switching means;

c) said plurality of data bus means; and

d) said parametric bus.

20. A programmable apparatus according to claim 19, further comprising:

e) timing function means for receiving timing signals from a timing generator and for controlling the sequential flow of at least said signal data in response thereto.

21. A programmable apparatus according to claim 20, further comprising:

f) at least one non-volatile programmable memory means, for storing topological and parametric data for said programmable apparatus.

22. A programmable apparatus according to claim 20, wherein:

at least part of said timing function means is associated with each of said plurality of functional blocks, wherein each of said plurality of functional blocks further comprise buffer means for storing signal data, and flag means for indicating to said timing function means that the associated functional block has finished processing signal data.

23. A programmable apparatus according to claim 19, wherein:

said plurality of functional block means comprises an analog to digital converter, a digital to analog converter, a serial input port, a serial output port, a plurality of filters, and a bidirectional parallel port.

24. A programmable apparatus according to claim 19, wherein:

said processing means of said core means distinguishes between topological data, parametric data, and signal data.

25. A programmable apparatus according to claim 20, wherein:

said timing function means provides cycles having a computational time period terminating in a transfer time period for at least said signal data, said functional block means provides an output during said transfer time periods.

26. A programmable apparatus according to claim 19, wherein:

said switch matrix means is dynamic such that said switch matrix means is configured in a first configuration during a first time period for switching said serial flow of signal data and is configured in a second configuration during a second time period for switching said serial flow of signal data.

27. A programmable system according to the claim 21, further comprising:

g) topology and parameter determination means for determining, in conjunction with a computer, a suitable topology for said programmable apparatus and suitable parameters for said functional block means in response to input into said computer by a user of desired programmable apparatus functioning, wherein said topology and parameter determination means is coupled to said communications bus, and said suitable topology and parameters are translated by said topology and parameter determination means into topological and parametric data, said topological data being forwarded to said at least one first memory means via said communications bus for storage.

28. A programmable system, comprising:

a) a communications bus;

b) a plurality of programmable apparatus, each said programmable apparatus capable of interfacing with said communication bus, and each said programmable apparatus comprising,

1) a plurality of functional block means, each said functional block means for performing an operation on signal data received by said functional block means,

2) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, matrix switching means for interconnecting at least two of said plurality of functional block means in a desired manner in response to said topological data received over said communications bus, wherein parametric data received by said processing means is sent by said processing means via a parametric bus to at least a first of said functional block means to control internal parameters of a least said first of said functional block means and wherein signal data is received by said plurality of functional block means via data busses coupled to said matrix switching means,

3) said plurality of data bus means, and

4) said parametric bus; and

c) linkage means for connecting at least two of said plurality of programmable apparatus.

29. A programmable system according to claim 28, wherein:

said core means further comprises timing function means for receiving timing signals from a timing generator and for controlling the sequential flow of at least said signal data in response thereto.

30. A programmable system according to claim 28, wherein:

said core means of each said plurality of programmable apparatus further comprises test function means for testing at least one of said functional block means to determine whether said at least one of said functional block means is functioning properly.

31. A programmable system according to claim 28, wherein:

each said programmable apparatus further comprises at least one non-volatile programmable memory means associated with said core means for storing topological and parametric data for said programmable apparatus.

32. A programmable system according to claim 28, wherein:

said linkage means carry at least said signal and timing data between said respective cores of said at least two of said plurality of programmable apparatus.

33. A programmable system according to claim 31, further comprising:

d) topology and parameter determination means for determining for each of said plurality of programmable apparatus, in conjunction with a computer, a suitable topology, and suitable parameters for said functional block means in response to input into said computer by a user of desired programmable system functioning, wherein said topology and parameter determination means is coupled to said communications bus, and said suitable topology and parameters are translated by said topology and parameter determination means into topological and parametric data and forwarded via said communications bus to said at least one programmable memory means for storage thereby.

34. A method for designing a custom programmable apparatus, said apparatus interfacing with a communications bus and having a plurality of functional block means having parameters for performing operations on received signal data, a core means for interfacing with said communications bus, for distinguishing between at least topological, signal, and parametric data received by said core means over said communications bus, and for signal flow interconnecting at least two of said plurality of functional block means in a desired manner, and a parametric bus means for carrying parametric information from said core means to said functional block means, said method comprising:

a) determining suitable signal flow interconnections of said plurality of functional blocks;

b) determining suitable parameters for said functional block means;

c) arranging said core means by coding said determined suitable signal flow interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections; and

d) providing said determined suitable parameters for said functional block means to said functional block means by coding said suitable parameters into second code and forwarding said second code via said communications bus, said core means and said parametric bus to a desired functional block means.

35. A method according to claim 34, wherein:

said steps of determining suitable signal flow interconnections and suitable parameters comprise inputting into a host processor controlling said communications bus indications of a desired transfer function for said apparatus, wherein said host processor is programmed to obtain said desired transfer function and to synthesize therefrom said suitable signal flow interconnections and said suitable parameters.

36. A method for designing a custom integrated circuit apparatus having a plurality of functional block means having desired parameters for performing desired operations on received signal data, and a core means interconnecting in a desired manner at least two of said plurality of functional block means for a desired sequential flow of signal data, said method comprising:

a) obtaining a programmable apparatus which interfaces with a communications bus, said apparatus having a plurality of functional block means for performing operations on received signal data, a core means for interfacing with said communications bus and for signal flow interconnecting at least two of said plurality of functional block means in a desired manner, and a parametric bus means for obtaining and carrying parametric data to said functional block means;

b) in conjunction with a host coupled to at least said communications bus and said programmable apparatus, determining suitable interconnections of said plurality of functional blocks of said programmable apparatus, and determining suitable parameters for said functional block means of said programmable apparatus;

c) arranging said core means of said programmable apparatus by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;

d) providing said determined suitable parameters for said functional block means to said functional block means of said programmable apparatus by coding said suitable parameters into second code and forwarding said second code via said parametric bus to desired functional block means of said programmable apparatus;

e) testing said programmable apparatus to determine whether said programmable apparatus is suitable for performing said desired operations;

f) finalizing core interconnection design and parameter values for said functional block means; and

g) producing integrated circuits based on said finalized interconnection design and based on said parameter values, said integrated circuit'"'"'s having at least a plurality of interconnected functional block means having said finalized parameter values which are functionally equivalent to those functional block means utilized in said finalizing step.