Programmable integrated analog input/output circuit with distributed matching memory array
First Claim
1. An integrated circuit for receiving and treating an analog signal exhibiting given signal attributes and for communicating with an external control component, comprising:
- a conditioning stage connectable to receive said analog signal to provide a conditioned analog signal;
an oversampling coder stage responsive to an oversampling control and to said conditioned analog signal to provide a corresponding coded serial bit stream output;
a decimating filter stage responsive to a decimating filter control and to said coded serial bit stream output to provide an output with a bit-defined information vector having a data aspect corresponding with said given signal attributes;
an interface port having a coupling portion connectable for communication with said external control component and an internal portion;
programming and data memory including a distributed memory matching array responsive to a conveyed instruction set having bit-defined codewords corresponding with a selected one of said signal attributes, responsive to a match control input to identify a correspondence between said information vector and at least one of said codewords to provide a digital result;
an output network responsive to said digital result to derive an output signal; and
a central control unit coupled in data exchange relationship with said interface port internal portion and said programming and data memory and responsive to derive said oversampling control, said decimating filter control, said match control input, and to effect conveyance of said instruction set to said distributed memory matching array.
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Accused Products
Abstract
A program controlled integrated circuit having an input path for receiving an analog signal with given attributes and using a program controlled sequence of treatment stages to generate a bit-defined information vector. That vector is introduced to a distributed memory matching array where it is compared with conveyed instruction set having bit-defned codewords corresponding with an analog signal attribute. A match process under the control of a central control unit then develops a digital result. The digital result may be utilized or converted to analog form in an analog return path. Both the input path and the return path incorporate a reduced instruction set computing arithmetic unit under the control of the central control unit.
35 Citations
42 Claims
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1. An integrated circuit for receiving and treating an analog signal exhibiting given signal attributes and for communicating with an external control component, comprising:
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a conditioning stage connectable to receive said analog signal to provide a conditioned analog signal;
an oversampling coder stage responsive to an oversampling control and to said conditioned analog signal to provide a corresponding coded serial bit stream output;
a decimating filter stage responsive to a decimating filter control and to said coded serial bit stream output to provide an output with a bit-defined information vector having a data aspect corresponding with said given signal attributes;
an interface port having a coupling portion connectable for communication with said external control component and an internal portion;
programming and data memory including a distributed memory matching array responsive to a conveyed instruction set having bit-defined codewords corresponding with a selected one of said signal attributes, responsive to a match control input to identify a correspondence between said information vector and at least one of said codewords to provide a digital result;
an output network responsive to said digital result to derive an output signal; and
a central control unit coupled in data exchange relationship with said interface port internal portion and said programming and data memory and responsive to derive said oversampling control, said decimating filter control, said match control input, and to effect conveyance of said instruction set to said distributed memory matching array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
said input conditioning stage includes a variable gain stage responsive to a conditioning signal to apply a select gain to said analog signal; and
said central control unit is responsive to derive said conditioning signal.
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3. The integrated circuit of claim 1 including:
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an arithmetic unit having an arithmetic unit input responsive to said decimating filter output and to an arithmetic unit control to provide said information vector; and
said central control unit is responsive to derive said arithmetic unit control.
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4. The integrated circuit of claim 1 in which:
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said oversampling coder stage is responsive to said conditioned analog signal to provide said coded serial bit stream output as a pulse density output; and
said decimating filter stage is a programmable counter filter.
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5. The integrated circuit of claim 1 in which said central control unit includes a program indexer sequentially actuable to access said programming memory for said oversampling control and said decimating filter control, and an instruction register for applying said accessed oversampling control and said decimating filter control respectively to said oversampling coder stage and said decimating filter stage.
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6. An integrated circuit of claim 1 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said decimating filter stage output and an arithmetic unit control input to arithmetically treat said decimating filter stage output and provide said bit-defined information vector at said arithmetic unit output; and
said central control unit is responsive to derive said arithmetic unit control input for application to said arithmetic unit input.
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7. The integrated circuit of claim 1 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said decimating filter stage output and an arithmetic unit control input to arithmetically treat said decimating filter stage output and provide said bit-defined information vector at said arithmetic unit output; and
said central control unit includes a program indexer actuable to access said programming memory for said oversampling control, said decimating filter control and said arithmetic unit control input, and an instruction register for applying said accessed oversampling control and said decimating filter control respectively to said oversampling coder stage and said decimating filter stage and for applying said arithmetic unit control input to said arithmetic unit input.
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8. The integrated circuit of claim 7 in which said arithmetic logic unit includes:
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an arithmetic status register coupled with said arithmetic unit output and said central control unit for conveying instantaneous operational status data thereto; and
a result register coupled with said arithmetic unit output and in feedback relationship with said arithmetic unit input and further coupled with said distributed memory matching array for conveying said bit-defined information vector thereto.
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9. The integrated circuit of claim 1 in which said distributed memory matching array comprises:
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a codeword address decoder and address bus responsive to a codeword address input for accessing said codewords from said data memory;
an input vector register responsive to said bit-defined information vector and a vector register control for combining said information vector and said accessed codewords in match calculation association within data memory and having match distance values in response to a match calculation instruction;
a match distance comparison circuit responsive to said match distance values to provide said digital result; and
said central control unit is responsive to effect provision of said codeword address input, and said vector register control and to effect application of said match distance values to said match distance comparison circuit.
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10. The integrated circuit of claim 9 in which said match distance comparison circuit is responsive to said match distance values to provide said digital result as one of said codewords.
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11. The integrated circuit of claim 9 in which:
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said central control unit includes a match distance program indexer actuable to access said programming memory for said distance comparison control; and
an instruction register coupled with said match distance comparison circuit for conveying said distance comparison control thereto.
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12. The integrated circuit of claim 11 in which:
said match distance comparison circuit includes a match status register coupled with said central control unit for conveying instantaneous operational status data thereto.
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13. The integrated circuit of claim 1 in which said output network comprises:
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an oversampling decoder stage responsive to a decoder control and to said digital result to provide an expanded digital word sample result with supplemented inter-word positions;
an interpolating filter stage responsive to an interpolator control and to said expanded digital word sample result to provide an interpolator output which provides a digital word defining signal having interpolated sample data values at said supplemental inter-word positions;
an analog signal formation stage responsive to said interpolator output to provide a corresponding analog output signal;
an output interface stage responsive to said analog output signal for providing a treated analog output; and
said central control unit is responsive to provide said decoder control and said interpolator control.
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14. The integrated circuit of claim 13 including:
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a reduced instruction set arithmetic unit having an input responsive to said interpolator output and to an arithmetic control to provide said digital word defining signal; and
said central control unit is responsive to derive said arithmetic control.
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15. The integrated circuit of claim 13 in which:
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said output interface stage includes a variable drive circuit responsive to an output conditioning signal to apply a select electrical parameter drive value to said analog output signal; and
said central control unit is responsive to derive said output conditioning signal.
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16. The integrated circuit of claim 13 in which:
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said distributed memory matching array includes an output register for conveying said digital result;
said oversampling decoder stage comprises a programmable zero fill up register, and said interpolating filter stage comprises a programmable interpolator.
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17. The integrated circuit of claim 13 in which:
said central control unit includes a program indexer actuable to access said programming memory for said decoder control and said interpolator control, and an instruction register for applying said accessed decoder control and interpolator control respectively to said oversampling decoder stage and said interpolating filter stage.
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18. The integrated circuit of claim 13 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said interpolating filter stage interpolator output and an arithmetic unit control input to arithmetically treat said interpolator output and provide said digital word defining signal at said arithmetic unit output; and
said central control unit is responsive to derive said arithmetic unit control input for application to said arithmetic unit input.
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19. The integrated circuit of claim 13 in which said analog signal formation stage comprises:
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a digital to pulse density stage responsive to said interpolator output to provide a serial bit stream signal having bit densities corresponding with said digital word defining signal;
a one-bit digital to analog converter responsive to said serial bit stream signal to provide a nascent analog signal; and
an analog low pass filter responsive to said nascent analog signal to derive said analog output signal.
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20. The integrated current of claim 13 in which said analog signal formation stage comprises:
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a digital to pulse density stage responsive to said interpolator output and to a pulse density control to provide a serial bit stream signal having bit densities corresponding with said digital word defining signal;
a one-bit digital to analog converter responsive to said serial bit stream signal to provide a nascent analog signal;
an analog low pass filter responsive to said nascent analog signal and a filter control to derive said analog output signal; and
said central control unit in responsive to derive said pulse density control and said filter control.
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21. The integrated circuit of claim 13 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said interpolating filter stage interpolator output and an arithmetic unit control input to arithmetically treat said interpolator output and provide said digital word defining signal at said arithmetic unit output; and
said central control unit includes a program indexer actuable to access said programming memory for said decoder control, said interpolator control and said arithmetic unit control input, and an instruction register for applying said accessed decoder control and said interpolator control respectively to said oversampling decoder stage and said interpolating filter stage and for applying said arithmetic unit control input to said arithmetic unit input.
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22. The integrated circuit of claim 21 in which said arithmetic logic unit includes:
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an arithmetic status register coupled with said arithmetic unit output and said central control unit for conveying instantaneous operational status data thereto; and
a result register coupled with said arithmetic unit output and in feedback relationship with said arithmetic unit input and further coupled with said analog signal formation stage for conveying said digital word defining signal.
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23. The integrated circuit of claim 13 in which said distributed memory matching array comprises:
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a codeword address decoder and address bus responsive to a codeword address input for accessing said codewords from said data memory;
an input vector register responsive to said bit-defined information vector and a vector register control for combining said information vector and said accessed codewords in match calculation association within data memory and having match distance values in response to a match calculation instruction;
a match distance comparison circuit responsive to said match distance values to provide said digital result as one of said codewords; and
said central control unit is responsive to effect provision of said codeword address input and said vector register control and to effect application of said match distance values to said match distance comparison circuit.
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24. An integrated circuit for receiving and treating an analog signal exhibiting given signal attributes and for communicating with an external control component, comprising:
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an input network connectable to receive said analog signal to provide a network output with a bit-defined information vector having a data aspect corresponding with at least one of said given signal attributes;
an interface port having a coupling portion connectable for communication with said external control component and an internal portion;
programming and data memory including a distributed memory matching array responsive to a conveyed instruction set having bit-defined codewords corresponding with a selected said signal attribute, responsive to a match control input to identify a correspondence between said information vector and one of said codewords to provide a digital result;
an oversampling decoder stage responsive to a decoder control and to said digital result to provide an expanded digital word sample result with supplemented inter-word positions;
an interpolating filter stage responsive to an interpolator control and to said expanded digital word sample result to provide an interpolator output which provides a digital word defining signal having interpolated sample data values at said supplemental inter-word positions;
an analog signal formation stage responsive to said interpolator output to provide a corresponding analog output signal;
an output interface stage responsive to said analog output signal for providing a treated analog output; and
a central control unit coupled in data exchange relationship with said interface port internal portion and said programming and data memory to provide said decoder control and said interpolator control. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
a reduced instruction set arithmetic unit having an input responsive to said interpolator output and to an arithmetic control to provide said digital word defining signal; and
said central control unit is responsive to derive said arithmetic control.
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26. The integrated circuit of claim 24 in which:
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said output interface stage includes a variable drive circuit responsive to an output conditioning signal to apply a select electrical parameter drive value to said analog output signal; and
said central control unit is responsive to derive said output conditioning signal.
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27. The integrated circuit of claim 24 in which:
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said distributed memory matching array includes an output register for conveying said digital result;
said oversampling decoder stage comprises a programmable zero fill up register, and said interpolating filter stage comprises a programmable interpolator.
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28. The integrated circuit of claim 24 in which:
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said central control unit includes a program indexer actuable to access said programming memory for said decoder control and said interpolator control, and an instruction register for applying said accessed decoder control and interpolator control respectively to said oversampling decoder stage and said interpolating filter stage.
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29. The integrated circuit of claim 24 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said interpolating filter stage interpolating output and an arithmetic unit control input to arithmetically treat said interpolator output and provide said digital word defining signal at said arithmetic unit output; and
said control unit is responsive to derive said arithmetic unit control input for application to said arithmetic unit input.
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30. The integrated circuit of claim 24 in which analog signal formation stage comprises:
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a digital to pulse density stage responsive to said interpolator output to provide a serial bit stream signal having bit densities corresponding with said digital word defining signal;
a one-bit digital to analog converter responsive to said serial bit stream signal to provide a nascent analog signal; and
an analog low pass filter responsive to said nascent analog signal to derive said analog output signal.
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31. The integrated circuit of claim 24 including:
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an arithmetic logic unit having an arithmetic unit input and an arithmetic unit output, responsive to said interpolating filter stage interpolator output and an arithmetic unit control input to arithmetically treat said interpolator output and provide said digital word defining signal at said arithmetic unit output; and
said central control unit includes a program indexer actuable to access said programming memory for said decoder control, said interpolator control and said arithmetic unit control input, and an instruction register for applying said accessed decoder control and said interpolator control respectively to said oversampling decoder stage and said interpolating filter stage and for applying said arithmetic unit control input to said arithmetic unit input.
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32. The integrated circuit of claim 31 in which said arithmetic logic unit includes:
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an arithmetic status register coupled with said arithmetic unit output and said central control unit for conveying instantaneous operational status data thereto; and
a result register coupled with said arithmetic unit output and in feedback relationship with said arithmetic unit input and further coupled with said analog signal formation stage for conveying said digital word defining signal.
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33. The integrated circuit of claim 24 in which said distributed memory matching array comprises:
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a codeword address decoder and address bus responsive to a codeword address input for accessing said codewords from said data memory;
an input vector register responsive to said bit-defined information vector and a vector register control for combining said information vector and said accessed codewords in match calculation association within data memory and having match distance values in response to a match calculation instruction;
a match distance comparison circuit responsive to said match distance values to provide said digital result as one of said codewords; and
said central control unit is responsive to effect provision of said codeword address input and said vector register control and to effect application of said match distance values to said match distance comparison circuit.
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34. A method for operating an integrated circuit to extract predetermined signal attributes from an analog signal applied to an input of said circuit, said method comprising the steps of:
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conditioning said analog signal at an input conditioning stage to provide a conditioned analog signal;
oversampling said conditioned analog signal with an oversampling coder operating under an oversampling control to provide a coded serial bit stream output;
filtering said coded serial bit stream with a decimation filter operating under a decimation filter control to derive a bit-defined information vector having a data aspect corresponding with said predetermined signal attributes;
providing a programming and data memory including a distributed memory matching array responsive to an instruction set and to a match control;
providing said instruction set in said programming and data memory, said instruction set having bit-defined codewords corresponding with said predetermined signal attribute;
matching said information vector with each of such bit-defined codewords under said match control to identify a correspondence between said information vector and one of said codewords to provide a digital result;
deriving said oversampling control, said decimation filter control and said match control with a central control unit provided as a component of said integrated circuit; and
generating an output signal corresponding with said digital result. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
comparing an unquantized signal corresponding with said digital result with said analog signal to derive an error value; and
adjusting said instruction set utilizing said central control unit in correspondence with said error value.
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40. The method of claim 34 in which said step of generating an output signal comprises the steps of:
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expanding said digital result with supplemental inter-word positions in correspondence with a decoder control to provide an expanded digital word sample result;
providing an interpolated sample data value at each said supplemental inter-word position under an interpolation control to derive an expanded digital result;
generating said decoder control and said interpolation control with said central control unit; and
converting said expanded digital result to an analog output signal.
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41. The method of claim 40 including the step of adjusting said expanded digital result with a reduced instruction set computing arithmetic unit operating under an arithmetic control derived at said central control unit.
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42. The method of claim 40 in which said step for converting said expanded digital result to an analog output signal comprises the steps of:
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converting said expanded digital result to a serial bit stream having bit densities corresponding therewith;
converting said serial bit stream to a nascent analog signal;
applying said nascent analog signal to a low pass filter to derive an analog signal; and
buffering said analog signal to derive said analog output signal.
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Specification