Microelectronic connections with liquid conductive elements

• US 6,202,298 B1
• Filed: 11/03/1997
• Issued: 03/20/2001
• Est. Priority Date: 05/02/1996
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Smith, John W.
• Primary Examiner(s): Young, Lee
• Assistant Examiner(s): Vereene, Kevin G.
• Application Number:
  US08/962,693
• Time in Patent Office: 1,233 Days
• Field of Search: 298/30, 298/40, 298/46, 298/52
• US Class Current: 29/840
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/02333 being a bump
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/8192 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49135 : and shaping, e.g., cutting or bending, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

A method of making a microelectronic assembly includes providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween and providing one or more masses of a fusible conductive material having a melting temperature below about 150° C. in said space, whereby the fusible conductive masses connect the first and second microelectronic elements to one another. Next, a flowable material is introduced between the confronting surfaces of the first and second microelectronic elements and around the one or more fusible conductive masses and the flowable material is then cured to provide a compliant layer disposed between said confronting surfaces and intimately surrounding each fusible conductive mass. The fusible conductive masses are capable of electrically interconnecting the contacts on microelectronic elements confronting one another and/or conducting heat between confronting microelectronic elements.

Claims

1. A method of making a microelectronic assembly comprising the steps of:

(a) providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween;

(b) providing one or more masses of a fusible conductive material having a melting temperature below about 65°

C. in said space;

then

(c) introducing a flowable material between the confronting surfaces of said first and second microelectronic elements and around said one or more conductive masses; and

(d) curing said flowable material to form a compliant layer disposed between said confronting surfaces and intimately surrounding each said conductive mass.

2. A method as claimed in claim 1, wherein said one or more fusible conductive masses are maintained in a substantially solid condition during said introducing a flowable material and said curing steps.

3. A method as claimed in claim 1, wherein said one or more conductive masses are maintained in a substantially liquid condition during said curing step.

4. A method as claimed in claim 1, wherein said first and second microelectronic elements include opposing contacts on said confronting surfaces, the step of providing one or more masses of said fusible conductive material including the step of disposing said fusible conductive masses between said opposing contacts for electrically interconnecting said first and second microelectronic elements to one another.

5. A method as claimed in claim 4, further comprising the step of providing a barrier layer between said contacts and said fusible conductive masses disposed thereon.

6. A method as claimed in claim 5, wherein said barrier layer includes polycrystalline silicon.

7. A method as claimed in claim 1 wherein said first and second microelectronic elements are circuit elements.

8. A method as claimed in claim 7, wherein said fusible conductive masses are capable of conducting electrical signals and heat between said first and second microelectronic elements.

9. A method as claimed in claim 7, wherein said second microelectronic element includes a flexible dielectric sheet having an exterior surface facing away from said first microelectronic element, said second microelectronic element including conductive terminals accessible at said exterior surface, the method further including the step of electrically connecting said terminals to said first microelectronic element.

10. A method as claimed in claim 9, further comprising the step of forcing said conductive terminals into substantially coplanar disposition while maintaining said fusible conductive masses in an at least partially molten condition.

11. A method as claimed in claim 9, wherein said connecting step includes the step of connecting said terminals to said first microelectronic element through flexible leads extending between said microelectronic elements.

12. A method as claimed in claim 11 wherein said microelectronic elements have contacts on their confronting surfaces, said step of electrically connecting said terminals to said first microelectronic element including the step of positioning at least some of said conductive masses between the contacts on said confronting surfaces so that such masses electrically connect contacts on said first and second microelectronic elements with one another.

13. A method as claimed in claim 11, wherein said fusible conductive masses are maintained in a substantially solid condition while said flowable material is introduced.

14. A method as claimed in claim 11, wherein said fusible conductive masses are maintained in a substantially liquid condition while said flowable material is introduced.

15. A method as claimed in claim 9, wherein said first microelectronic element includes a plurality of semiconductor chips and said connecting step includes the step of electrically connecting said plurality of chips to conductive elements on to said flexible dielectric sheet.

16. A method as claimed in claim 15 wherein said conductive elements on said flexible dielectric sheet include conductive traces and said connecting step is performed so that said traces interconnect at least some of said chips with one another.

17. A method as claimed in claim 15, wherein said first microelectronic element includes said plurality of semiconductor chips, each said chip being aligned with a portion of said dielectric sheet, the method further including the step of severing said portions of said sheet and separating said chips from one another to thereby form individual chip assemblies each including one said chip and the portion of said dielectric sheet aligned therewith.

18. A method as claimed in claim 17, wherein said first microelectronic element includes a unitary wafer incorporating said plurality of semiconductor chips, said step of separating said chips from one another including the step of severing said wafer.

19. A method as claimed in claim 1 wherein said first microelectronic element includes one or more semiconductor chips and said second microelectronic element includes a thermally conductive package element, and wherein said conductive masses are thermally conductive.

20. A method as claimed in claim 19 further comprising the step of moving said one or more semiconductor chips relative to said package element while said conductive masses are in a substantially liquid condition.

21. A method as claimed in claim 1, wherein said first microelectronic element has a front face and a rear face, said step of providing said first and second elements being performed so that said second microelectronic element confronts said front face of said first microelectronic element and defines a front space therebetween, said conductive masses being provided in said front space, the method further comprising the steps of:

providing a third microelectronic element confronting said rear surface so that said first microelectronic element and said third microelectronic element define a rear space between said rear surface and said third microelectronic element;

disposing one or more fusible conductive masses having a melting temperature below about 150°

C. in said rear space; and

introducing a flowable material into said rear space and around said conductive masses in said rear space.

22. A method as claimed in claim 21, further comprising the step of curing said flowable material in said rear space to form a rear compliant layer between said third microelectronic element and said first microelectronic element, said rear compliant layer intimately surrounding said conductive masses in said rear space.

23. A method as claimed in claim 22 wherein said step of introducing said flowable material into said rear space and said step of introducing said flowable material between the confronting surfaces of said first and second microelectronic elements are preformed by introducing simultaneously using a single flowable material.

24. A method as claimed in claim 22 wherein said first microelectronic element includes a semiconductor chip, said second microelectronic element includes a circuit panel, and said third microelectronic element includes a thermally conductive element.

25. A method as claimed in claim 21 further comprising the step of moving said second and third microelectronic elements toward one another while said masses in said front and rear spaces are in a molten condition to thereby compress material in said front and rear spaces.

26. A method as claimed in claim 25 wherein said second microelectronic element is a flexible dielectric sheet having an exterior surface facing away from said first microelectronic element, said second microelectronic element including conductive terminals accessible at said exterior surface, the method further including the step of electrically connecting said terminals to said first microelectronic element.

27. A method as claimed in claim 1, wherein said fusible conductive material has a melting temperature below about 125°

C.

28. A method as claimed in claim 1, wherein said fusible conductive material has a melting temperature below about 65°

C.

29. A method as claimed in claim 1, wherein said fusible conductive material has a melting temperature between about 25°

C. and about 65°

C.

30. A method as claimed in claim 1, wherein said fusible conductive material includes a metal.

31. A method as claimed in claim 1, wherein said fusible conductive material includes a metal alloy.

32. A method as claimed in claim 1, further comprising the step of applying a polymer coating to said one or masses of said fusible conductive material before the introducing a flowable material step.

33. A method as claimed in claim 32, wherein said polymer coating includes polyparaxylene.

34. A method of making a microelectronic assembly comprising the steps of:

(a) juxtaposing in spaced apart relationship a microelectronic first element with a second element having electrically conductive areas;

(b) providing one or more masses of a fusible conductive material extending between said first and second elements, said fusible conductive material having a melting temperature below about 65°

C.;

(c) introducing a flowable material between said first and second elements; and

(d) curing said flowable material to form a compliant layer disposed between said first and second elements and intimately surrounding said fusible conductive masses.

35. A method as claimed in claim 34, wherein said microelectronic first element includes contacts, and said one or more masses of a fusible conductive material are in contact within said contacts and said electrically conductive areas of said second element.

36. The method as claimed in claim 35, wherein said second element comprises a second microelectronic element.

37. The method as claimed in claim 34, wherein said second element comprises a metallic plate.

38. The method as claimed in claim 37, further including the steps of forming a layer on a first side of said metallic plate, said layer having apertures therein and including a material which is non-wettable by said conductive masses and exposing said first side of said plate to said conductive masses while said conductive masses are in molten condition so that drops of said fusible conductive masses adhere to said metallic plate at said apertures.

39. A method of making a microelectronic assembly comprising the steps of:

(a) providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween;

(b) providing one or more masses of a fusible conductive material having a melting temperature below about 150°

C. in said space;

then

(c) introducing a flowable material between the confronting surfaces of said first and second microelectronic elements and around said one or more conductive masses; and

(d) curing said flowable material to form a compliant layer disposed between said confronting surfaces and intimately surrounding each said conductive mass, wherein said one or more fusible conductive masses are maintained in a substantially liquid condition during said step of introducing a flowable material.

40. A method as claimed in claim 39, wherein one or more conductive masses are maintained in said substantially liquid condition during said curing step.

41. A method as claimed in claim 39, wherein said first and second microelectronic elements include opposing contacts on said confronting surfaces, the step of providing one or more masses of said fusible conductive material including the step of disposing said fusible conductive masses between said opposing contacts for electrically interconnecting said first and second microelectronic elements to one another.

42. A method as claimed in claim 41, further comprising the step of providing a barrier layer between said contacts and said fusible conductive masses disposed thereon.

43. A method as claimed in claim 42, wherein said barrier layer includes polycrystalline silicon.

44. A method as claimed in claim 39, wherein said first and second microelectronic elements are circuit elements.

45. A method as claimed in claim 44, wherein said fusible conductive masses are capable of conducting electrical signals and heat between said first and second microelectronic elements.

46. A method as claimed in claim 44, wherein said second microelectronic element includes a flexible dielectric sheet having an exterior surface facing away from said first microelectronic element, said second microelectronic element including conductive terminals accessible at said exterior surface, the method further including the step of electrically connecting said terminals to said first microelectronic element.

47. A method as claimed in claim 46, further comprising the step of forcing said conductive terminals into substantially coplanar disposition while maintaining said fusible conductive masses in an at least partially molten condition.

48. A method as claimed in claim 46, wherein said connecting step includes the step of connecting said terminals to said first microelectronic element through flexible leads extending between said microelectronic elements.

49. A method as claimed in claim 48, wherein said microelectronic elements have contacts on their confronting surfaces, said step of electrically connecting said terminals to said first microelectronic element including the step of positioning at least some of said conductive masses between the contacts on said confronting surfaces so that said masses electrically connect contacts on said first and second microelectronic elements with one another.

50. A method as claimed in claim 46, wherein said first microelectronic element includes a plurality of semiconductor chips and said connecting step includes the step of electrically connecting said plurality of chips to conductive elements on to said flexible dielectric sheet.

51. A method as claimed in claim 50, wherein said conductive elements on said flexible dielectric sheet include conductive traces and said connecting step is performed so that said traces interconnect at least some of said chips with one another.

52. A method as claimed in claim 50, wherein said first microelectronic element includes said plurality of semiconductor chips, each said chip being aligned with a portion of said dielectric sheet, the method further including the step of severing said portions of said sheet and separating said chips from one another to thereby form individual chip assemblies each including one said chip and the portion of said dielectric sheet aligned therewith.

53. A method as claimed in claim 52, wherein said first microelectronic element includes a unitary wafer incorporating said plurality of semiconductor chips, said step of separating said chips from one another including the step of severing said wafer.

54. A method as claimed in claim 39, wherein said first microelectronic element includes one or more semiconductor chips and said second microelectronic element includes a thermally conductive package element, and wherein said conductive masses are thermally conductive.

55. A method as claimed in claim 54, further comprising the step of moving said one or more semiconductor chips relative to said package element while said conductive masses are in a substantially liquid condition.

56. A method as claimed in claim 39, wherein said first microelectronic element has a front face and a rear face, said step of providing said first and second elements being performed so that said second microelectronic element confronts said front face of said first microelectronic element and defines a front space therebetween, said conductive masses being provided in said front space, the method further comprising the steps of:

providing a third microelectronic element confronting said rear surface so that said first microelectronic element and said third microelectronic element define a rear space between said rear surface and said third microelectronic element;

disposing one or more fusible conductive masses having a melting temperature below about 150°

C. in said rear space; and

introducing a flowable material into said rear space and around said conductive masses in said rear space.

57. A method as claimed in claim 56, further comprising the step of curing said flowable material in said rear space to form a rear compliant layer between said third microelectronic element and said first microelectronic element, said rear compliant layer intimately surrounding said conductive masses in said rear space.

58. A method as claimed in claim 57, wherein said step of introducing said flowable material into said rear space and said step of introducing said flowable material between the confronting surfaces of said first and second microelectronic elements are preformed by introducing simultaneously using a single flowable material.

59. A method as claimed in claim 57, wherein said first microelectronic element includes a semiconductor chip, said second microelectronic element includes a panel, and said third microelectronic element includes a thermally conductive element.

60. A method as claimed in claim 56, further comprising the step of moving said second and third microelectronic elements toward one another while said masses in said front and rear spaces are in a molten condition to thereby compress material in said front and rear spaces.

61. A method as claimed in claim 60, wherein said second microelectronic element is a flexible dielectric sheet having an exterior surface facing away from said first microelectronic element, said second microelectronic element including conductive terminals accessible at said exterior surface, the method further including the step of electrically connecting said terminals to said first microelectronic element.

62. A method as claimed in claim 39, wherein said fusible conductive material has a melting temperature between about 25°

C. and about 65°

C.

63. A method as claimed in claim 39, wherein said fusible conductive material includes a metal.

64. A method as claimed in claim 39, further comprising the step of applying a polymer coating to said one or masses of said fusible conductive material before the introducing a flowable step.

65. A method of making a microelectronic assembly comprising the steps of:

(a) juxtaposing in spaced apart relationship a microelectronic first element with a second element having electrically conductive areas;

(b) providing one or more masses of a fusible conductive material extending between said first and second elements;

(c) introducing a flowable material between said first and second elements; and

(d) curing said flowable material to form a compliant layer disposed between said first and second elements and intimately surrounding said fusible conductive masses, wherein said one or more fusible conductive masses are maintained in a substantially liquid condition during said step of introducing a flowable material.

66. A method as claimed in claim 65, wherein said microelectronic first element includes contacts, and said one or more masses of a fusible conductive material are in contact within said contacts and said electrically conductive areas of said second element.

67. The method as claimed in claim 66, wherein said second element comprises a second microelectronic element.

68. The method as claimed in claim 65, wherein said second element comprises a metallic plate.

69. The method as claimed in claim 68, further including the steps of forming a layer on a first side of said metallic plate, said layer having apertures therein and including a material which is non-wettable by said conductive masses and exposing said first side of said plate to said conductive masses while said conductive masses are in molten condition so that drops of said fusible conductive masses adhere to said metallic plate at said apertures.

70. A method as claimed in claim 65, wherein one or more conductive masses are maintained in said substantially liquid condition during said curing step.