Semiconductor device and method of manufacture

• US 6,204,097 B1
• Filed: 03/01/1999
• Issued: 03/20/2001
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Robb, Stephen P., Robb, Francine Y., Shen, Zheng
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Smith, Bradley
• Application Number:
  US09/259,602
• Time in Patent Office: 750 Days
• Field of Search: 438/133, 438/135, 438/140, 438/137, 438/138
• US Class Current: 438/133
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor material having an active region and a field relaxation region;

forming a plurality of doped regions of a first conductivity type in the active region of the semiconductor material, wherein doped regions of the plurality of doped regions are spaced apart from each other by regions of the semiconductor material that are of a second conductivity type; and

forming a plurality of trenches in the active region underlying the doped regions of a first conductivity type, and a plurality of trenches in the field relaxation region providing an edge termination structure in the semiconductor material.

2. The method of claim 1, wherein the step of providing the semiconductor material includes epitaxially growing silicon of the second conductivity type and a first dopant concentration on a body of silicon of the second conductivity type and a second dopant concentration, the first dopant concentration being less than the second dopant concentration.

3. The method of claim 1, wherein the step of forming the plurality of trenches includes using at least one doped region of the plurality of doped regions, wherein the at least one doped region surrounds an active region of the semiconductor material.

4. The method of claim 3, further comprising forming an insulated gate semiconductor device in the active region.

5. The method of claim 4, wherein the step of forming an insulated gate semiconductor device includes forming one of an insulated gate field effect transistor or an insulated gate bipolar transistor as the insulated gate semiconductor device.

6. The method of claim 1, wherein the step of forming the plurality of doped regions includes

filling each of the plurality of trenches with polysilicon, the polysilicon being of the first conductivity type.

7. The method of claim 1, wherein the step of forming the plurality of doped regions includes

filling each of the plurality of trenches with an epitaxial material, the epitaxial material being of the first conductivity type.

8. The method of claim 1, wherein the step of forming the plurality of trenches includes forming a plurality of substantially concentric field-limiting rings, including an inner most field-limiting ring, an outermost field-limiting ring, and at least one field limiting ring between an innermost field-limiting ring and the outermost field-limiting ring.

9. A method for manufacturing a power semiconductor device, comprising the steps of:

providing a body of semiconductor material having first and second major surfaces, an active region, and a field relaxation region;

forming a plurality of trenches in the active region and a plurality of trenches in the field relaxation region;

filling the plurality of trenches in the active region and the plurality of trenches in the field relaxation region with a semiconductor material of a first conductivity type;

forming a gate structure over the first major surface and a portion of the source region; and

forming a source region in the active region.

10. The method of claim 9, further including the step of contacting the source region with a first conductive material and contacting the second major surface with a second conductive material.

11. The method of claim 9, wherein the step of providing the body of semiconductor material includes:

providing a semiconductor substrate of a second conductivity type and a first dopant concentration; and

forming a first layer of semiconductor material of the second conductivity type and a second concentration on the semiconductor substrate.

12. The method of claim 11, further including forming second layer of semiconductor material of the second conductivity type and a third dopant concentration on the second layer of semiconductor material.

13. The method of claim 9, wherein the step of providing the body of semiconductor material includes:

providing a semiconductor substrate of the first conductivity type and a first dopant concentration; and

forming a layer of semiconductor material of a second conductivity type and a second dopant concentration on the semiconductor substrate.

14. The method of claim 9, wherein the step of providing the body of semiconductor material includes:

providing a semiconductor substrate of the first conductivity type and a first dopant concentration;

forming a buffer layer of a second conductivity type and a second dopant concentration on the semiconductor substrate; and

forming a drift layer of the second conductivity type and a third dopant concentration on the buffer layer.

15. The method of claim 9, wherein the step of filling the plurality of trenches includes planarizing the material used to fill the plurality of trenches.

16. The method of claim 9, further including forming an electrical contact to the field relaxation region.

17. The method of claim 9, wherein the steps of forming the plurality of trenches includes using a Reactive Ion Etch technique to form the plurality of trenches.

18. A method for manufacturing a trench semiconductor device having a substrate with a first major surface, comprising the steps of:

forming an active region and a field relaxation region in the substrate;

forming a gate structure in the active region, and on the first major surface of the substrate; and

filling at least one trench in the active region and at least one trench in the field relaxation region with a material of a first conductivity type to form the trench semiconductor device.

19. The method of claim 18, further including forming a field relaxation region contact overlying the field relaxation region.

20. The method of claim 18, further including forming a shallow doped region of a first conductivity type.

21. The method of claim 20, further including forming a first contact overlying the shallow doped region.

22. The method of claim 18, further including forming an epitaxial layer of a second conductivity type and a second dopant concentration.

23. The method of claim 22, wherein the substrate is of the second conductivity type and a first dopant concentration.

24. The method of claim 18, wherein the filling step includes one of a polysilicon material or an epitaxial material.