Method for establishing shallow junction in semiconductor device to minimize junction capacitance

• US 6,204,157 B1
• Filed: 01/07/2000
• Issued: 03/20/2001
• Est. Priority Date: 12/07/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ibok, Effiong
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/479,492
• Time in Patent Office: 438 Days
• Field of Search: 438/585, 438/510, 438/514, 438/517, 438/528, 438/556, 438/559
• US Class Current: 438/528
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: Y10S 438/918 Special or nonstandard dopant

Abstract

A method for making a semiconductor device including a silicon substrate includes implanting Nitrogen into the substrate after gate stack formation and before source/drain pant implantation. The Nitrogen is implanted and then annealed as appropriate to establish shallow junction regions and minimal overlap regions in the substrate. Then, the source/drain dopant is implanted and activated, with the dopant essentially being constrained by the Nitrogen to remain concentrated in the shallow junction and minimal overlap regions, thereby minimizing junction capacitance and overlap capacitance in the finished device and consequently improving the speed of operation of the device.

Claims

1. A method for fabricating a semiconductor device, the semiconductor device including a substrate, the method comprising:

establishing plural transistor gate stacks on the substrate such that at least one prospective junction region is defined in the substrate between two adjacent stacks, the prospective junction region defining a desired lower bound;

disposing Nitrogen into the prospective junction region;

annealing the substrate to cause the Nitrogen to agglomerate at a depth greater than the desired lower bound;

implanting dopant into the prospective junction region;

then

annealing the substrate to activate dopant.

2. The method of claim 1, wherein the act of implanting dopant includes implanting the dopant to a depth of at least the desired lower bound.

3. The method of claim 1, further comprising annealing the substrate after the act of disposing the Nitrogen and before the act of implanting the dopant.

4. The method of claim 1, further comprising:

determining a desired minimal overlap region under the gate stacks; and

establishing an annealing time and temperature for annealing the substrate with Nitrogen in response to the determining act, such that overlap capacitance is minimized.

5. The method of claim 4, wherein the act of annealing the substrate after Nitrogen disposition is established to cause the Nitrogen to diffuse and thereby establish the minimal overlap regions.