Method of making integrated circuit capacitor including tapered plug

• US 6,204,186 B1
• Filed: 07/30/1999
• Issued: 03/20/2001
• Est. Priority Date: 01/13/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Chaudhry, Samir, Layadi, Nace, Vaidya, Hem M., Roy, Pradip Kumar, Chetlur, Sundar Srinivasan
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): CHEN, KIN CHAN
• Application Number:
  US09/364,366
• Time in Patent Office: 599 Days
• Field of Search: 257/295, 257/296, 257/306, 438/238, 438/239, 438/240, 438/241, 438/253-256, 438/700, 438/701, 438/713
• US Class Current: 438/700
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.

Claims

1. A method of making a capacitor comprising the steps of:

forming an interconnection line above a substrate;

depositing a first dielectric layer on the interconnection line;

etching a via in the first dielectric layer, the via having a tapered width which increases in a direction toward the substrate;

filling the via with a conductive metal to form a metal plug;

etching a trench in the first dielectric layer around an upper portion of the metal plug;

depositing a second dielectric layer adjacent the metal plug; and

depositing an upper electrode layer on the second dielectric layer.

2. A method according to claim 1, further comprising the step of depositing a lower electrode layer lining the trench and contacting the metal plug.

3. A method according to claim 1, wherein the step of etching the via comprises the use of directional etching.

4. A method according to claim 1, wherein the tapered width of the via has an angle of taper greater than about 2°

.

5. A method according to claim 1, wherein the tapered width of the via has an angle of taper greater than about 5°

.

6. A method according to claim 5, wherein the upper portion of the metal plug also has a tapered width which increases in the direction toward the substrate.

7. A method according to claim 1, wherein the metal plug comprises a lower portion disposed in the first dielectric layer and having a tapered width which increases in the direction toward the substrate.

8. A method according to claim 1, wherein the step of etching the trench comprises etching the trench to a depth of more than one half a thickness of the first dielectric layer.

9. A method according to claim 1, wherein the metal plug is connected to the interconnection line.

10. A method according to claim 1, further comprising the step of planarizing an uppermost surface of the metal plug and an adjacent uppermost surface of the first dielectric layer.

11. A method of making an integrated circuit capacitor comprising the steps of:

forming a first dielectric layer adjacent a substrate;

forming a metal plug comprising

an upper portion extending toward an uppermost surface of the first dielectric layer, and

a lower portion disposed in the first dielectric layer and having a tapered width which increases in a direction toward the substrate;

forming a trench in the first dielectric layer around the upper portion of the metal plug;

forming a second dielectric layer adjacent the metal plug; and

forming an upper electrode layer on the second dielectric layer.

12. A method according to claim 11, further comprising the step of depositing a lower electrode layer lining the trench and contacting the metal plug.

13. A method according to claim 11, wherein the upper portion of the metal plug also has a tapered width which increases in the direction toward the substrate.

14. A method according to claim 11, wherein the tapered width of the lower portion of the metal plug has an angle of taper greater than about 2°

.

15. A method according to claim 11, wherein the tapered width of the lower portion of the metal plug has an angle of taper greater than about 5°

.

16. A method according to claim 11, wherein the step of forming the trench comprises forming the trench to a depth greater than about half a thickness of the first dielectric layer.

17. A method according to claim 11, wherein the step of forming the trench comprises firming the trench to a depth greater than about 250 angstroms.

18. A method according to claim 11, further comprising the step of forming an interconnection line extending below the first dielectric layer and connected to the metal plug.

19. A method according to claim 11, further comprising the step of planarizing an uppermost surface of the metal plug and an adjacent uppermost surface of the first dielectric layer.

20. A method according to claim 11, wherein the step of forming the metal plug comprises the steps of:

etching a via in the first dielectric layer, the via having a tapered width which increases in the direction toward the substrate; and

filling the via with a conductive metal.

21. A method according to claim 20, wherein the conductive metal comprises tungsten.

22. A method of making an integrated circuit capacitor comprising:

forming a first dielectric layer adjacent a substrate;

forming a metal plug having a tapered width which increases in a direction toward the substrate;

forming a trench in the first dielectric layer to a depth greater than about half a thickness of the first dielectric layer;

forming a second dielectric layer adjacent the metal plug; and

forming an upper electrode layer on the second dielectric layer.

23. A method according to claim 22, further comprising the step of depositing a lower electrode layer lining the trench and contacting the metal plug.

24. A method according to claim 22, wherein the step of forming the metal plug comprises the steps of:

etching a via in the first dielectric layer, the via having a tapered width which increases in the direction toward the substrate; and

filling the via with a conductive metal.

25. A method according to claim 22, wherein the tapered width of the via has an angle of taper greater than about 2°

.

26. A method according to claim 22, wherein the tapered width of the via has an angle of taper greater than about 5°

.

27. A method according to claim 22, further comprising the step of forming an interconnection line extending below the first dielectric layer and connected to the metal plug.

28. A method according to claim 22, further comprising the step of forming an upper most surface of the upper portion of the metal plug substantially coplanar with an adjacent uppermost surface of the first dielectric layer.

29. A method according to claim 22, wherein the step of forming the trench comprises forming the trench to a depth greater than about 250 angstroms.