Two signal one power plane circuit board

• US 6,204,453 B1
• Filed: 12/02/1998
• Issued: 03/20/2001
• Est. Priority Date: 12/02/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lauffer, John M., Markovich, Voya R., Wilson, William E., Magnuson, Roy H., Perrino, Marybeth, Paoletti, Jim P., Memis, Irv, Keesler, Ross W., Jimarez, Miguel A., Fallon, Kenneth, Welsh, John A.
• Primary Examiner(s): Sough, Hyung-Sub
• Assistant Examiner(s): NORRIS, JEREMY C
• Application Number:
  US09/203,956
• Time in Patent Office: 839 Days
• Field of Search: 174/261, 174/262, 174/263, 174/266, 174/264, 174/265, 174/255, 361/744, 361/765
• US Class Current: 174/255
• CPC Class Codes: H05K 1/056 the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2201/09554 Via connected to metal substrate
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/44 Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits H05K3/0058, H05K3/4608, and H05K3/4641 take precedence
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core

Abstract

A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

Claims

1. A printed circuit card comprising a single metal layer sandwiched between a pair of dielectric layers, said dielectric layers each being formed of a photoimaged cured dielectric material and each having an outer edge, a border surrounding said circuit card, said border being comprised of said metal layer terminating at a distance spaced from the edge of one of the dielectric layers and adjacent the edge of said other dielectric layer;

metallization on each of said first and second layers forming circuitry on said first and second layers of said photoimageable material, and blind vias completely filled with metal in said first and second layers of photoimageable material connected to said circuitry and terminating at said metal layer.

2. The invention as defined in claim 1 further characterized by a plated through hole extending through each layer of dielectric material and through the metal layer.

3. The invention as defined in claim 2 wherein said plated through hole is electrically connected to the circuitry on both dielectric materials.

4. The invention as defined in claim 1 wherein a plurality of circuit boards comprise a panel connected by the borders at said one dielectric layer of material.

5. The invention as defined in claim 1 wherein the layer of metal is copper.

6. The invention as defined in claim 1 wherein the circuitry is copper.