Non-volatile memory structure and corresponding manufacturing process

• US 6,204,531 B1
• Filed: 07/29/1999
• Issued: 03/20/2001
• Est. Priority Date: 07/30/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pio, Federico, Dalla Libera, Giovanna
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H
• Application Number:
  US09/363,429
• Time in Patent Office: 600 Days
• Field of Search: 257/326, 257/288, 257/314, 257/315, 257/316, 257/319, 257/324
• US Class Current: 257/326
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate. The floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching. In one preferred method, a contact to the control gate is formed above the active area.

Claims

1. A semiconductor non-volatile memory device comprising:

a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and

a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors,

wherein each memory cell is coupled to a bit line that is formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region, and

the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to a first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

2. The memory device as defined in claim 1, wherein the contact to the control gate is substantially aligned with a central portion of the active area.

3. The memory device as defined in claim 1,

wherein the floating gate and control gate are formed with double-poly wings that are symmetric with respect to the active area, and

the contact to the control gate is located above the double-poly wings.

4. The memory device as defined in claim 1, wherein the memory device is formed by a process that includes the step of:

defining the floating gate using only a POLY2 mask and a Self-Aligned poly2/interpoly/poly1 stack etching.

5. The memory device as defined in claim 1, wherein the device is a Flash-EEPROM.

6. A semiconductor non-volatile memory device comprising:

a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above a field oxide region and not above the active area; and

a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors,

wherein each memory cell is coupled to a bit line that is formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region, and

the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to a first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

7. A semiconductor non-volatile memory device comprising:

at least one memory cell including a floating gate transistor that has an active area source and drain regions, a floating gate, and a control gate;

at least one selection transistor serially coupled to the floating gate transistor;

a control gate line formed by at least a first metal interconnection layer, the control gate line being electrically connected to the control gate of the memory cell by a contact that is located above the active area; and

a bit line formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region,

wherein the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to the first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

8. The memory device as defined in claim 7, wherein the contact to the control gate is substantially aligned with a central portion of the active area.

9. The memory device as defined in claim 7, wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and

the contact to the control gate is located above the double-poly wings.

10. The memory device as defined in claim 7, wherein a metal layer island is provided around the other contact.

11. An information handling system including at least one semiconductor non-volatile memory device, said memory device comprising:

a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and

a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors,

wherein each memory, cell is coupled to a bit line that is formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region, and

the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to a first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

12. The information handling system as defined in claim 11, wherein the contact to the control gate is substantially aligned with a central portion of the active area.

13. The information handling system as defined in claim 11,

wherein the floating gate and control gate are formed with double-poly wings that are symmetric with respect to the active area, and

the contact to the control gate is located above the double-poly wings.