Semiconductor device and method for making the same

• US 6,204,564 B1
• Filed: 11/20/1998
• Issued: 03/20/2001
• Est. Priority Date: 11/21/1997
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Miyata, Osamu, Shibata, Kazutaka, Ueda, Shigeyuki
• Primary Examiner(s): Crane, Sara
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/196,884
• Time in Patent Office: 851 Days
• Field of Search: 257/785, 257/737, 257/738, 257/786, 257/778, 257/783, 257/730, 257/780, 257/779, 257/789, 257/795
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29399 Coating material
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/8319 : Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/83951 : Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/556 : against alpha rays
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device comprising a film substrate and a semiconductor chip bonded to an upper surface of the film substrate is provided. The semiconductor chip has a main surface formed with a plurality of terminal pads. The film substrate has a lower surface formed with a plurality of external terminal portions in a matrix pattern, and an upper surface formed with a plurality of wiring patterns for respectively connecting with the external terminal portions. The wiring patterns formed in the upper surface of the film substrate are respectively connected to the terminal pads formed on the main surface of the semiconductor chip.

Claims

1. A semiconductor device comprising:

A film substrate having an upper surface and a lower surface, the upper surface being provided with a plurality of wiring patterns, the lower surface being provided with a plurality of external terminal portions which are arranged in a matrix pattern and connected with the wiring patterns;

a semiconductor chip having a main surface provided with a plurality of bump terminal pads, and an upper surface opposite to the main surface, the semiconductor chip being mounted on the film substrate with the bump terminal pads held in facing relation to the wiring patterns;

a connection layer made of an anisotropic conductive adhesive arranged between the semiconductor chip and the film substrate for mechanically connecting the chip to the substrate and for electrically connecting the bump terminal pads to the wiring pattern; and

an insulating film formed on the upper surface of the film substrate for covering at least part of the wiring patterns in a manner avoiding the bump terminal pads.

2. The semiconductor device according to claim 1, wherein each of the external terminal portions includes a solder ball placed in a hole formed in the film substrate, part of the solder ball projecting out of the hole beyond the lower surface of the film substrate, the hold being closed at an end thereof by a part of a corresponding one of the wiring patterns, the solder ball being bonded to said part of the corresponding one of the wiring patterns.

3. The semiconductor device according to claim 1, wherein the anisotropic conductive adhesive includes a porous resin.

4. The semiconductor device according to claim 3, wherein the porous resin is a thermosetting phenol resin.

5. The semiconductor device according to claim 1, wherein a circumferential portion of the anisotropic conductive adhesive and side surfaces of the semiconductor chip are surrounded by a protective resin.

6. The semiconductor device according to claim 5, wherein the protective resin includes a porous resin.

7. The semiconductor device according to claim 5, wherein the protective resin rides on upper surface of the semiconductor chip.

8. The semiconductor device according to claim 1, wherein each of the wiring patterns is provided with a first end portion and a second end portion, the first end portion being electrically connected to a corresponding one of the external terminal portions, the second end portion being electrically connected to a corresponding one of the bump terminal pads which is displaced from said corresponding one of the external terminal portions in a plan view.

9. The semiconductor device according to claim 8, wherein each of the terminal pads of the semiconductor chip is disposed in a circumferential edge portion of the main surface of the semiconductor chip, the external terminal portions being located inwardly of each of the terminal pads in a plan view.

10. The semiconductor device according to claim 1, wherein the insulating film is an alpha ray shielding insulation coating.

11. The semiconductor device according to claim 10, wherein the alpha ray shielding insulation coating is formed at least in a region right above each of the external terminal portions.

12. The semiconductor device according to claim 10, wherein the alpha ray shielding insulation coating is made of a polyimide resin.

13. The semiconductor device according to claim 10, wherein the semiconductor chip is a memory chip including a memory cell domain.

14. The semiconductor device according to claim 1, wherein the upper surface of the semiconductor chip is essentially exposed, at least part of a circumferential region of the upper surface being chamfered.

15. The semiconductor device according to claim 1, wherein the upper surface of the semiconductor ship is essentially exposed, the upper surface being formed with fine serration and marked by printing.

16. The semiconductor device according to claim 1, wherein the upper surface of the semiconductor chip is covered by a resin coating marked by printing.