Method and structure for configuring FPGAS

• US 6,204,687 B1
• Filed: 08/13/1999
• Issued: 03/20/2001
• Est. Priority Date: 08/13/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Schultz, David P., Goetting, F. Erich, Hung, Lawrence C.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/374,434
• Time in Patent Office: 585 Days
• Field of Search: 326/38-41, 326/46, 326/47
• US Class Current: 326/40
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected to the bus including a frame data register, a frame address register, a control register, a command register, and an optional data check register. The bus interface generates control signals in response to the address field and the operand field that cause one or more registers to perform predefined operations according to subsequent data words in the bit stream. For example, during configuration write operations, the bus interface enables the frame data register to receive data signals that are subsequently transferred to a configuration memory array. Conversely, during configuration read operations, the frame data register is controlled to receive data from the configuration memory array, and to transfer the data to the bus interface. Partial reconfiguration is performed by storing the address of selected frames of the configuration memory array in the frame address register, which addresses the selected frames in the configuration memory array.

Claims

1. A programmable logic device including:

a plurality of configurable logic blocks connected by configurable interconnect resources;

a configuration memory array including a plurality of cells coupled to the configurable logic blocks and the configurable interconnect resources;

an input terminal for receiving a configuration bit stream including a header word and a second word;

a bidirectional configuration bus;

a plurality of configuration registers respectively having first data terminals connected to the bidirectional configuration bus and second data terminals connected to the configuration memory array; and

a bus interface circuit connected between the input terminal and the bidirectional configuration bus, the bus interface circuit including an address decoder for decoding an register address field from the header word and for transmitting a register enable signal to a selected configuration register when the register address field matches a predetermined address value assigned to the selected configuration register, wherein the selected configuration register is enabled by the register enable signal to receive the second word from the data bus.

2. A method for programming a programmable logic device, the programmable logic device including a plurality of configurable logic blocks connected by configurable interconnect resources, a configuration memory array including a plurality of cells coupled to the configurable logic blocks and the configurable interconnect resources, and one or more input terminals for receiving a configuration bit stream including a header word and a configuration data word, wherein the method comprises:

parsing the header word to identify a register address field;

transmitting a register enable signal to a selected configuration register of a plurality of configuration registers when the register address field matches a predetermined address value assigned to the selected configuration register, thereby enabling the selected configuration register to receive the configuration data word; and

transmitting the configuration data word to the selected register on a bus that is connected to the plurality of configuration registers.

3. A method for reading a configuration data word from a programmable logic device, the programmable logic device including a plurality of configurable logic blocks connected by configurable interconnect resources, a configuration memory array including a plurality of cells including a group of cells storing the configuration data word, the plurality of cells being coupled to the configurable logic blocks and the configurable interconnect resources, wherein the method comprises:

transmitting a frame address to a frame address register on a bus, the frame address register being connected to the configuration memory array, wherein the frame address register generates address signals in response to the frame address that cause the configuration memory array to address the group of cells storing the configuration data word; and

transmitting the configuration data word from the configurable memory array to the bus.