Clock-gating circuit for reducing power consumption

• US 6,204,695 B1
• Filed: 06/18/1999
• Issued: 03/20/2001
• Est. Priority Date: 06/18/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ching, Alvin Y., Wong, Jennifer, Young, Steven P., Alfke, Peter H., Frake, Scott O.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, M.
• Application Number:
  US09/336,357
• Time in Patent Office: 641 Days
• Field of Search: 326/93, 327/141
• US Class Current: 326/93
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Claims

1. A method of gating a clock signal in a user-defined logic device, the method comprising the steps of:

providing a clock signal to a storage latch of the user-defined logic device, wherein the clock signal transitions between a first logic state and a second logic state;

providing a clock enable signal to the storage latch;

enabling the storage latch to provide a gate control signal representative of the clock enable signal while the clock signal is in the first logic state;

latching the clock enable signal in the storage latch when the clock signal transitions from the first logic state to the second logic state, wherein the clock enable signal remains latched in the storage latch as long as the clock signal remains in the second logic state, the storage latch providing the gate control signal with a value representative of the latched clock enable signal while the clock signal remains in the second logic state;

controlling the gating of the clock signal on the user-defined logic device with the gate control signal; and

routing the clock signal to an array of configurable logic blocks of the user-defined logic device through a global routing circuit of the user-defined logic device, thereby programmably controlling the configurable logic blocks.

2. A clock gating circuit in a user-defined logic device including an array of configurable logic blocks, the clock gating circuit comprising:

an input terminal for receiving an input clock signal;

an input terminal for receiving a clock enable signal;

a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal;

a logic gate coupled to receive the input clock signal and the clock gate control signal, wherein the logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal; and

a global routing circuit for routing the output clock signal to the array of configurable logic blocks,

wherein the array of configurable logic blocks is programmably controlled by the output clock signal.

3. The clock gating circuit of claim 2, wherein the clock gating circuit is located outside the array of configurable logic blocks.

4. The clock gating circuit of claim 2, wherein the clock gating circuit is configured by memory cells.

5. The clock gating circuit of claim 2, wherein the storage latch has a data terminal coupled to receive the clock enable signal and a latch enable terminal coupled to receive the input clock signal.

6. The clock gating circuit of claim 2, wherein the logic gate comprises an AND gate.

7. A clock gating circuit comprising:

an input terminal for receiving an input clock signal;

an input terminal for receiving a clock enable signal;

a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal;

a NAND gate coupled to receive the input clock signal and the clock gate control signal; and

an inverter coupled to receive an output signal from the NAND gate, wherein the NAND gate selectively routes the input clock signal in response to the clock gate control signal, the inverter thereby providing the output clock signal.

8. A clock gating circuit comprising:

an input terminal for receiving an input clock signal;

an input terminal for receiving a clock enable signal;

a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal;

a programmable memory cell storing a logic value;

a first NAND gate coupled to receive the clock gate control signal and a logic value equal to the inverse of the logic value stored within the programmable memory cell;

a second NAND gate coupled to receive the clock gate control signal and the logic value stored within the programmable memory cell;

an AND gate coupled to receive the input clock signal and an output signal from the first NAND gate;

a first inverter coupled to receive an output signal from the second NAND gate;

a NOR gate coupled to receive an output signal of the AND gate and an output signal of the first inverter; and

a second inverter coupled to receive an output signal of the NOR gate, the second inverter thereby providing the output clock signal.