Power amplifier

• US 6,204,731 B1
• Filed: 04/30/1999
• Issued: 03/20/2001
• Est. Priority Date: 12/05/1998
• Status: Active Grant

• Current Assignee: Wipro Limited
• Original Assignee: OKI Techno Centre Pte Limited
• Inventors: Nakamura, Hiroshi, Xinwei, Wang, Jiang, Cao
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/302,858
• Time in Patent Office: 690 Days
• Field of Search: 330/295, 330/296, 330/302, 330/310, 330/51, 330/124.R, 330/136
• US Class Current: 330/310
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/408 the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence

Abstract

A power amplifier has an input terminal for receiving a signal to be amplified and an output terminal to which the amplified signal is passed, and comprises single stage which-, or a plurality of cascaded amplifier stages one of, which-, is formed from a plurality of amplifiers connected in parallel with their input ports interconnected and their output ports interconnected. Said one stage may be the last stage. In one arrangement said one stage comprises two or more amplifiers at least one of which is biased at class AB and at least another of which is biased at class C. Alternatively said one stage comprises two or more amplifiers at least one of which is biased at class AB and at least another of which may be switchably biased at class AB or class C.

Again, alternatively, the said one stage may comprise two or more amplifiers, each of which may be switchably biased at class AB or class C and the gates widths of which may be different. The amplifier stages may comprise bipolar junction transistors or field effect transistors. Means are preferably provided enabling the power to be divided to the input to each amplifier in said one stage and means enabling the outputs of each of said amplifiers to be combined. There may be provided between the power dividing point to the input of each of said amplifiers a matching circuit enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers. In said one stage there may be provided between the output ports of each of said amplifiers and the combining point a matching circuit enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.

Claims

1. A power amplifier having an input terminal for receiving an input signal to be amplified and an output terminal to which the amplified signal is passed, the power amplifier comprising a plurality of cascaded amplifier stages one of which comprises a plurality of amplifiers connected in parallel with their input ports interconnected and their output ports interconnected;

and

said plurality of amplifiers connected in parallel defining at least a class AB amplifier and a class C amplifier, wherein if the power level of the input signal is below a predetermined input signal, then the class AB amplifier alone is operational and if the power level of the input signal transitions above the predetermined input signal, then both the class AB and class C amplifiers are operational.

2. An amplifier as claimed in claim 1, wherein said one stage is the last stage in said plurality of cascaded amplifier stages.

3. An amplifier as claimed in claim 1, wherein said one stage comprises two or more amplifiers at least one of which is biased at class AB and at least another of which may be switchably biased at class AB or class C.

4. An amplifier as claimed in claim 3, arranged such that the amplifier with switchable bias is biased at class C when the power level of the input signal is low, and at class AB when the power level of the input signal is high.

5. An amplifier as claimed in claim 1, wherein said one stage comprises two or more amplifiers each of which may be switchably biased at class AB or class C and the gates of widths of which are different.

6. An amplifier as claimed in claim 5 arranged such that the FET with a smaller gate width is biased at class AB and the other at class C when the input power is low, but the amplifier who'"'"'s FET with a larger gate width is biased at class AB and the others are biased at class C when the input power level is medium and in which all the amplifiers are biased to class AB when the input power level is HIGH.

7. An amplifier as claimed in claim 2, wherein the amplifiers in said one stage comprise different threshold voltage biased field effect transistors having the same gate bias voltages.

8. An amplifier as claimed in claim 1, wherein said amplifier stages are formed of bipolar junction transistors.

9. An amplifier as claimed in claim 1, wherein said amplifier stages are formed of field effect transistors.

10. An amplifier as claimed in claim 1 including means enabling the power to be divided to the input to each amplifier in said one stage.

11. An amplifier as claimed in claim 1 including means enabling the outputs of each of said amplifiers to be combined.

12. An amplifier as claimed in claim 1 wherein there is provided between the power dividing point to the input of each of said amplifiers and matching circuit means enabling phase shifting to compensate for the amplitude a phase response of each of said amplifiers.

13. An amplifier as claimed in claim 1 wherein in said final stage there is provided between the output port of each of said amplifiers and the combining point a matching circuit means enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.

14. A power amplifier having an input terminal for receiving a signal to be amplified and an output terminal to which the amplified signal is passed, and which comprises a plurality of amplifiers connected in parallel with their input ports interconnected and their output ports interconnected;

wherein said plurality of amplifiers connected in parallel includes a first amplifier and a second amplifier; and

wherein the first amplifier alone is operational when the input signal is below a predetermined level, and both the first and second amplifiers are operational when the signal is above the predetermined level.

15. An amplifier as claimed in claim 14, wherein there are provided two or more amplifiers at least one of which is biased at class AB and at least another of which is biased at class C.

16. An amplifier as claimed in claim 15, arranged such that when the power level of the input signal is low the class AB amplifier alone is operational and when the power level of the input signal becomes high both the class AB and class C amplifiers are operational.

17. An amplifier as claimed in claim 14, wherein there are provided two or more amplifiers at least one of which is biased at class AB and at least another of which may be switchably biased at class AB or class C.

18. An amplifier as claimed in claim 17, arranged such that the amplifier with switchable bias is biased at class C when the power level of the input signal is low, and at class AB when the power level of the input signal is high.

19. An amplifier as claimed in claim 14, wherein there are provided two or more amplifiers each of which may be switchably biased at class AB or class C and the gates widths of which are different.

20. An amplifier as claimed in claim 19 arranged such that the FET with a smaller gate width is biased at class AB and the other at class C when the input power is low, but the amplifier who'"'"'s FET with a wider gate is biased at class AB and the others are biased at class C when the input power level is medium and in which all the amplifiers are biased to class AB when the input power level is HIGH.

21. An amplifier as claimed in claim 14, wherein the amplifiers comprise different threshold voltage field effect transistors having the same gate bias voltages.

22. A power amplifier as claimed in claim 14 wherein said amplifiers are formed of bipolar junction transistors.

23. An amplifier as claimed in claim 14, wherein said amplifiers are formed of FETs.

24. An amplifier as claimed in claim 14, including means enabling the power to be divided to the input to each amplifier and means enabling the outputs of each of said amplifiers to be combined.

25. An amplifier as claimed in claim 14, wherein there is provided between the power dividing point to the input of each of said amplifiers and matching circuit means enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.

26. An amplifier as claimed in claim 14, wherein there is provided between the output ports of each of said amplifiers and the combining point a matching circuit enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.

27. An amplifier according to claim 14, wherein the first amplifier is class AB and the second amplifier is class C.

29. A method according to claim 27, wherein the first amplifier is a class AB amplifier.

30. A method according to claim 27;

wherein the second amplifier is a class C amplifier.

31. A method according to claim 27, wherein the gate voltage for the first amplifier is set to a value higher than its pinch off voltage.

32. A method according to claim 27, wherein the gate voltage for the second amplifier is set to a value lower than its pinch-off voltage.

28. A method for amplifying a signal comprising the steps of:

biasing a first amplifier at a predetermined level;

biasing a second amplifier at a level that is different from the predetermined level of the first amplifier;

coupling the first and second amplifiers in parallel; and

applying an input signal to the first and second amplifiers coupled in parallel, wherein the first amplifier alone is substantially operational when the input signal is below a predetermined level and the first and the second amplifiers are both substantially operational when the input signal is above the predetermined level.