Circuit for the acquisition of binary analog signals

• US 6,204,786 B1
• Filed: 04/14/1999
• Issued: 03/20/2001
• Est. Priority Date: 04/17/1998
• Status: Expired due to Fees

• Current Assignee: Sextant Avionique
• Original Assignee: Sextant Avionique
• Inventors: Prost, Michel, Pitot, Christian, Bieth, Philippe
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US09/291,044
• Time in Patent Office: 706 Days
• Field of Search: 327/205, 327/206, 341/133, 323/259, 710/128, 710/129, 604/67
• US Class Current: 341/133
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03K 3/0377 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

The disclosure relates to the acquisition of a binary analog signal at input of a digital integrated circuit after its range of voltage variation has been matched with that acceptable by the digital integrated circuit by means of a resistive divider bridge. It is usual to define the architecture of an ASIC digital integrated circuit on the basis of libraries of pre-characterized cells. The disclosed device is designed to increase the possibilities of choice open to the integrated circuit designer, in enabling him to one pre-characterized cell of a Schmitt trigger for its top switching threshold and another for its bottom switching threshold. It consists of a circuit comprising, at input, a bank of Schmitt triggers of different types, followed by a discrete-rendering logic circuit deducing the logic state of the binary input analog signal of the combination of the output states of the input Schmitt triggers.

Claims

1. A circuit for the acquisition of a binary analog signal comprising, at input, at least two Schmitt triggers with staged top and bottom switching thresholds parallel-connected by their inputs and followed at output by at least one discrete-rendering logic circuit that changes state, on the one hand, when the Schmitt trigger with the highest top switching threshold passes to the logic 1 level and, on the other hand, when the Schmitt trigger with the lowest bottom switching threshold passes to the logic 0 level.

2. A circuit according to claim 1, wherein the discrete-rendering logic circuit is an AND type logic gate.

3. A circuit according to claim 1, wherein the discrete-rendering logic circuit is a storage register with a data input D placed at the logic +1 level, a write-enable input e connected to the output of one of the Schmitt triggers and a priority zero-resetting complemented input nr connected to the output of the other of the Schmitt triggers.

9. A circuit according to claim 1 or claim 4, furthermore comprising a malfunction-detection logic circuit that is parallel-connected at input to the discrete-rendering logic circuit and detects the forbidden combinations between output states of the different input Schmitt triggers.

10. A circuit according to claim 9, wherein the malfunction-detection logic circuit generates an alarm signal in the event of the maintenance of forbidden combinations between output states of the different input Schmitt triggers beyond a certain duration.

11. A circuit according to claim 1 or claim 4, forming part of an encapsulated integrated circuit, wherein the circuit has its different input Schmitt triggers connected at input to one and the same connection pin of the pack of the digital integrated circuit.

12. A circuit according to claim 1 or claim 4, several circuits of this kind forming part of one and the same encapsulated digital integrated circuit, wherein the encapsulated integrated circuit is equipped with means for the individual testing of each of the thresholds of the Schmitt triggers of the different circuits of the same kind, said testing means being based on sequences of NAND type logic gates each connected to the outputs of one and the same type of Schmitt trigger.

13. A circuit according to claim 1 or claim 4, furthermore comprising a noise-preventive digital filter connected to the output of the discrete-rendering logic circuit.

14. A circuit according to claim 1 or claim 4, comprising several different discrete-rendering logic circuits parallel-connected to the outputs of the input Schmitt triggers and followed by a circuit for the selection of the output signal of one of them.

4. A circuit for the acquisition of a binary analog signal comprising, at input, at least two Schmitt triggers with staged top and bottom switching thresholds parallel-connected by their inputs and followed at output by at least one discrete-rendering logic circuit that changes state, on the one hand, when the Schmitt trigger with the highest bottom switching threshold passes to the logic 0 level and, on the other hand, when the Schmitt trigger with the lowest top switching threshold passes to the logic 1 level, and comprising a feedback circuit which, for a brief instant, force the Schmitt trigger with the highest top switching threshold to cross its top threshold as soon as the input signal has crossed the top threshold of the other Schmitt trigger in the upward direction, and force the Schmitt trigger with the lowest bottom switching threshold to cross its bottom threshold as soon as the input signal has crossed the bottom threshold of the other Schmitt trigger in the downward direction.

5. A circuit according to claim 4, wherein the feedback circuit comprises:

at least one output digital circuit configured to send one of the logic 0 level and the logic 1 level to at least one of the Schmitt triggers;

at least one output logic gate configured to send a first signal to the at least one output digital circuit; and

an input logic gate configured to receive a second signal from the at least one discrete-rendering logic circuit and send a third signal to the at least one output logic gate.

6. A circuit according to claim 5, wherein the at least one output logic gate and the input logic gate are AND type logic gates.

7. A circuit according to claim 4, wherein the discrete-rendering logic circuit is an OR type logic gate.

8. A circuit according to claim 4, wherein the discrete-rendering logic circuit is a storage register with a data input D placed at the logic +1 level, a write-enable input e connected to the output of one of the Schmitt triggers and a priority zero-resetting complemented input nr connected to the output of the other of the Schmitt triggers.