Variable resistor circuit and a digital-to-analog converter

• US 6,204,789 B1
• Filed: 09/06/2000
• Issued: 03/20/2001
• Est. Priority Date: 09/06/1999
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nagata, Mitsuru
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/656,434
• Time in Patent Office: 195 Days
• Field of Search: 341/144, 341/143, 341/145, 341/154, 341/153, 341/139, 341/110, 341/113, 323/354, 338/334
• US Class Current: 341/144
• CPC Class Codes: H03M 3/346 by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation

Abstract

A 1-bit D/A converter with a zero detect soft mute function is provided in such a manner that a counter is operated by detecting that a multibit digital signal is all zero for a constant period of time, and a feedback resistor of an op-amp in the analog low-pass filter is decreased stepwise based on a discrete value of the counter so as to be finally short-circuited so that a D/A convert output is fixed at a reference potential. The feedback resistor is composed of a plurality of resistors of first and second groups and first to third analog switches. A first digital control variable resistor is constituted by connecting the resistors of the first group in series and connecting a first analog switch selectively turned on/off in accordance with an output signal other than an LSB of the counter to respective nodes. A second digital control variable resistor is constituted by connecting the resistors of the second group in parallel and connecting a second analog switch controlled by the LSB of the counter to one side resistor in series. The first and second digital control variable resistors are connected in series, and a third analog switch is connected to both ends so as to constitute a feedback resistor.

Claims

1. A variable resistor circuit of digital control comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with an output signal other than an output signal corresponding to an LSB of a counter;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having two resistors connected in parallel and a second digital control switch connected to one side resistor in series, said second digital control switch being on/off controlled by the output signal corresponding to the LSB of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

2. The variable resistor circuit according to claim 1, wherein the resistance of the i resistors among the first digital control variable resistor and the resistance of the two resistors among the second digital control variable resistor are substantially equal to each other.

3. The variable resistor circuit according to claim 1, wherein each of the group of first digital control switches and the second digital control switch is composed of solely an N channel MOS transistor or solely a P channel MOS transistor, and the third digital control switch is composed of a combination of the N channel MOS transistor and the P channel MOS transistor.

4. A 1-bit D/A converter with a zero detect soft mute function wherein a multibit digital signal is converted into a 1-bit signal, the 1-bit signal is analog outputted through an inverting amplifier type analog low-pass filter, a counter is operated by detecting that the multibit digital signal is all zero for a constant period of time, and a feedback resistor of the inverting amplifier in the analog low-pass filter is decreased stepwise based on a discrete value of the counter so as to be finally short-circuited so that a D/A convert output is fixed at a reference potential, said feedback resistor comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with an output signal other than an output signal corresponding to an LSB of the counter;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having two resistors connected in parallel and a second digital control switch connected to one side resistor in series, said second digital control switch being on/off controlled by the output signal corresponding to the LSB of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

5. The D/A converter according to claim 4, wherein the resistance of the i resistors among the first digital control variable resistor and the resistance of the two resistors among the second digital control variable resistor are substantially equal to each other.

6. The D/A converter according to claim 4, wherein each of the group of first digital control switches and the second digital control switch is composed of solely an N channel MOS transistor or solely a P channel MOS transistor, and the third digital control switch is composed of a combination of the N channel MOS transistor and the P channel MOS transistor.

7. A variable resistor circuit of digital control comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with output signals corresponding to bits of a counter, other than an LSB and a second LSB;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having four resistors connected in parallel and a group of second digital control switches in which each switch is connected to three resistors among the four resistors in series, respectively, said group of second digital control switches being on/off controlled by the output signal corresponding to bits the LSB and the second LSB of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

8. The variable resistor circuit according to claim 7, wherein the resistance of the i resistors among the first digital control variable resistor and the resistance of the resistors to which the group of second digital control switches are not connected in series among the second digital control variable resistor are r and are substantially equal to each other, and the resistances of the three resistors to which the group of second digital control switches are connected in series are 3r, r, r/3, respectively.

9. The variable resistor circuit according to claim 7, wherein each of the group of first digital control switches and the group of second digital control switches is composed of solely N channel MOS transistors or solely P channel MOS transistors, and the third digital control switch is composed of a combination of the N channel MOS transistor and the P channel MOS transistor.

10. A 1-bit D/A converter with a zero detect soft mute function wherein a multibit digital signal is converted into a 1-bit signal, the 1-bit signal is analog outputted through an inverting amplifier type analog low-pass filter, a counter is operated by detecting that the multibit digital signal is all zero for a constant period of time, and a feedback resistor of the inverting amplifier in the analog low-pass filter is decreased stepwise based on a discrete value of the counter so as to be finally short-circuited so that a D/A convert output is fixed at a reference potential, said feedback resistor comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with output signals corresponding to bits of the counter, other than an LSB and a second LSB;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having four resistors connected in parallel and a group of second digital control switches in which each switch is connected to three resistors among the four resistors in series, respectively, said group of second digital control switches being on/off controlled by the output signal corresponding to bits the LSB and the second LSB of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

11. The D/A converter according to claim 10, wherein the resistance of the i resistors among the first digital control variable resistor and the resistance of the resistors to which the group of second digital control switches are not connected in series among the second digital control variable resistor are r and are substantially equal to each other, and the resistances of the three resistors to which the group of second digital control switches are connected in series are 3r, r, r/3, respectively.

12. The D/A converter according to claim 10, wherein each of the group of first digital control switches and the group of second digital control switches is composed of solely an N channel MOS transistor or solely a P channel MOS transistor, and the third digital control switch is composed of a combination of the N channel MOS transistor and the P channel MOS transistor.

13. A variable resistor circuit of digital control comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with output signals of an upper bit side of a counter;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having p resistors (p is a positive integral number which is two or greater) connected in parallel and a group of second digital control switches connected to (p−

1) resistors among the p resistors in series, respectively, said group of second digital control switches being on/off controlled by output signals of a lower bit side of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

14. A 1-bit D/A converter with a zero detect soft mute function wherein a multibit digital signal is converted into a 1-bit signal, the 1-bit signal is analog outputted through an inverting amplifier type analog low-pass filter, a counter is operated by detecting that the multibit digital signal is all zero for a constant period of time, and a feedback resistor of the inverting amplifier in the analog low-pass filter is decreased stepwise based on a discrete value of the counter so as to be finally short-circuited so that a D/A convert output is fixed at a reference potential, said feedback resistor comprising:

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with output signals of an upper bit side of the counter;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having p resistors (p is a positive integral number which is two or greater) connected in parallel and a group of second digital control switches connected to (p−

1) resistors among the p resistors in series, respectively, said group of second digital control switches being on/off controlled by output signals of a lower bit side of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

15. A 1-bit D/A converter with a zero detect soft mute function comprising:

a sigma-delta modulator to which a multibit digital signal is inputted and which converts the multibit digital signal into an m level signal and outputs the m level signal;

an m level DAC to which the m level signal outputted from the sigma-delta modulator is inputted,

an analog low-pass filter to which an analog output outputted from the m level DAC is inputted so as to output an analog signal, said analog low-pass filter having an inverting amplifier;

a zero detect circuit detecting that the multibit digital signal is all zero for a constant period of time;

an n-bit up/down counter starting an up-count operation when it is detected that the multibit digital signal is all zero for a constant period of time by the zero detect circuit and starting a down-count operation at the time of non-detecting;

a decoder to which an n-bit discrete value outputted from the up/down counter is inputted and which decodes the n-bit discrete value so as to generate a substantially 2<sup>n−

1</sup> decode signal; and

a feedback resistor being controlled by the substantially 2<sup>n−

1</sup> decode signal outputted from the decoder so that its resistance is decreased stepwise to be short-circuited finally, said feedback resistor comprising;

a first digital control variable resistor in which a combined resistance changes stepwise, said first digital control variable resistor having i resistors (i is a positive integral number which is two or greater) connected in series and a group of first digital control switches each provided between one end of the obtained combined resistor and one end of one resistor, said group of first digital control switches being on/off controlled selectively in accordance with output signals of an upper bit side of a counter;

a second digital control variable resistor connected to the first digital control variable resistor in series, said second digital control variable resistor having p resistors (p is a positive integral number which is two or greater) connected in parallel and a group of second digital control switches connected to (p−

1) resistors among the p resistors in series, respectively, said group of second digital control switches being on/off controlled by output signals of a lower bit side of the counter; and

a third digital control switch provided between both ends of the first and second digital control variable resistors connected in series, said third digital control switch being ON controlled when the counter becomes a specific value so as to short-circuit both ends of the first and second digital control variable resistors.

16. The D/A converter according to claim 15, wherein the p is two, and the second digital control switch is on/off controlled by an output signal corresponding to an LSB of the counter.

17. The D/A converter according to claim 15, wherein the p is four, and the second digital control switches are on/off controlled by output signals corresponding to bits an LSB and a second LSB of the counter.

18. The D/A converter according to claim 15, wherein each of the group of first digital control switches and the group of second digital control switches is composed of solely an N channel MOS transistor or solely a P channel MOS transistor, and the third digital control switch is composed of a combination of the N channel MOS transistor and the P channel MOS transistor.

19. The D/A converter according to claim 18, wherein the third digital control switch comprises a first MOS transistor of the N channel type having one end of a current path connected to a first terminal, the other end of the current path connected to a second terminal, a gate connected to receive a switch control signal, and a back gate connected to a ground point, a second MOS transistor of the P channel type having one end of a current path connected to the first terminal, the other end of the current path connected to the second terminal, and a gate connected to receive an inverted signal of the switch control signal, a third MOS transistor of the N channel type having one end of a current path connected to a back gate of the second MOS transistor, the other end of the current path connected to the second terminal, a gate connected to receive the switch control signal, and a back gate connected to the ground point, a fourth MOS transistor of the P channel type having one end of a current path connected to the back gate of the second MOS transistor, the other end of the current path connected to the second terminal, a gate connected to receive the inverted signal of the switch control signal, and a back gate connected to a power supply, and a fifth MOS transistor of the P channel type having one end of a current path connected to the back gate of the second MOS transistor, the other end of the current path connected to the power supply, and a gate connected to receive the switch control signal.

20. The D/A converter according to claim 18, wherein the third digital control switch comprises a first MOS transistor of the N channel type having one end of a current path connected to a first terminal, the other end of the current path connected to a second terminal, a gate connected to receive a switch control signal, and a back gate connected to the ground point, and a second MOS transistor of the P channel type having one end of a current path connected to the first terminal, the other end of the current path connected to the second terminal, a gate connected to receive an inverted signal of the switch control signal, and a back gate connected to the power supply.

21. The D/A converter according to claim 15, wherein the resistance of the i resistors among the first digital control variable resistor and the resistance of the resistors to which the second digital control switches are not connected in series among the second digital control variable resistor are substantially equal to each other.

22. The D/A converter according to claim 15, wherein the m level DAC outputs an m level DC value from an analog output terminal, the analog low-pass filter comprises a plurality of resistors connected in series between an inverting input terminal of the inverting amplifier and the analog output terminal of the m level DAC and a plurality of capacitors connected between the nodes of the plurality of resistors and ground point, respectively.

23. The D/A converter according to claim 15, wherein the m level DAC outputs an m level DC value in accordance with levels of m output terminals, and the analog low-pass filter comprises an m group resistors in which a plurality of resistors are connected in series to each other and m capacitors connected between the nodes of the m group resistors and ground point, respectively, said m group resistors being connected between the inverting input terminal of the inverting amplifier and the m output terminals.

24. The D/A converter according to claim 15, further comprising a capacitor connected between an output terminal and an inverting input terminal of the inverting amplifier.

25. The D/A converter according to claim 15, further comprising a reference voltage generating circuit applying a reference potential to an non-inverting input terminal of the inverting amplifier.