Single transistor cell, method for manufacturing the same, memory circuit composed of single transistor cells, and method for driving the same
First Claim
1. A memory circuit formed of single cell transistors comprising unit circuits arranged to form a cell array, each unit circuit further comprising first and second cell transistors,wherein a source of the first cell transistor and a source of the second cell transistor are connected in common to a drive line, a drain of the first cell transistor is connected to a first bit line, a drain of the second cell transistor is connected to a second bit line, a gate of the first cell transistor is connected to a first word line, a gate of the second cell transistor is connected to a second word line, and ferroelectric layers of the first and second cell transistors are connected in common to a plate line.
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Abstract
A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.
15 Citations
7 Claims
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1. A memory circuit formed of single cell transistors comprising unit circuits arranged to form a cell array, each unit circuit further comprising first and second cell transistors,
wherein a source of the first cell transistor and a source of the second cell transistor are connected in common to a drive line, a drain of the first cell transistor is connected to a first bit line, a drain of the second cell transistor is connected to a second bit line, a gate of the first cell transistor is connected to a first word line, a gate of the second cell transistor is connected to a second word line, and ferroelectric layers of the first and second cell transistors are connected in common to a plate line.
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3. A method for driving a memory circuit, comprising:
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writing a “
1”
to an arbitrary cell byapplying a voltage V to a plate line connected to a ferroelectric layer, grounding a word line connected to a gate of a cell transistor of said arbitrary cell facing the ferroelectric layer, and floating a drive line connected to a source of the cell transistor and a bit line connected to a drain of the cell transistor;
writing a “
0”
to said arbitrary cell, byapplying a voltage V to the plate line, applying a voltage V to the word line, and floating the drive line and the bit line; and
reading data stored in said arbitrary cell, by applying a voltage V to the drive line, and measuring a current induced in the bit line. - View Dependent Claims (4, 5, 6)
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7. A method for driving a memory circuit, comprising:
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writing a “
1”
to an arbitrary cell byapplying a voltage V to a plate line connected to a ferroelectric layer, applying a voltage −
V to a word line connected to a gate of a cell transistor of said arbitrary cell facing the ferroelectric layer, andfloating a drive line connected to a source of the cell transistor and a bit line connected to a drain of the cell transistor;
writing a “
0”
to said arbitrary cell, byapplying a voltage −
V to the plate line,applying a voltage V to the word line, and floating the drive line and the bit line; and
reading data stored in said arbitrary cell, by applying a voltage V to the drive line, and measuring a current induced in the bit line.
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Specification
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- Resources
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Current AssigneeSamsung Electronics Co. Ltd. (Samsung Group)
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Original AssigneeSamsung Electronics Co. Ltd. (Samsung Group)
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InventorsLee, Jong-ho
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Primary Examiner(s)Elms, Richard
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Assistant Examiner(s)Nguyen, Tuan T.
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Application NumberUS09/459,916Time in Patent Office462 DaysField of Search365/145, 365/65, 257/295US Class Current365/145CPC Class CodesG11C 11/22 using ferroelectric elementsG11C 11/223 using MOS with ferroelectri...H01L 29/6684 with a ferroelectric gate i...H01L 29/78391 the gate comprising a layer...
