ATM cell scheduler which uses a heap memory and associates timestamps with each channel

• US 6,205,151 B1
• Filed: 12/18/1997
• Issued: 03/20/2001
• Est. Priority Date: 11/21/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Karguth, Brian J., Prasad, Sharat, Quay, Jeffrey R.
• Primary Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US08/993,801
• Time in Patent Office: 1,188 Days
• Field of Search: 370/395, 370/232, 370/235, 370/236, 370/230, 370/412, 370/468, 370/224, 370/411, 370/413-416
• US Class Current: 370/416
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (38), and indicates to a source behavior processor (24) in the scheduler (14) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (12) to effect the transmission as appropriate.

Claims

1. A method of scheduling the transmission of packet cells associated with a plurality of communications channels, comprising the steps of:

sorting channel entries in a heap memory, each channel entry comprising a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, the sorting step identifying a root channel entry corresponding to the next due channel;

comparing the timestamp value of the root channel entry to a global time generated by a reference timer; and

responsive to the comparing step determining that the global time has at least reached the timestamp value of the root channel entry, issuing a transmit credit for the channel associated with the root channel entry.

2. The method of claim 1, further comprising:

after the step of issuing a transmit credit, retrieving an allowed cell rate value from a parameter memory for the channel associated with the root channel entry;

deriving a new timestamp value for the channel associated with the root channel entry; and

then repeating the sorting, comparing, and issuing steps.

6. The method of claim 1, wherein the sorting step comprises:

identifying first and second groups of the plurality of channels, the first group of the plurality of channels having timestamp values that are nearer due than the timestamp values of the second group of the plurality of channels;

storing channel entries for the first group of the plurality of channels in a first parameter memory; and

storing channel entries for the second group of the plurality of channels in a second parameter memory.

8. The method of claim 1, further comprising:

after the step of issuing a transmit credit, retrieving an allowed cell rate value for the one of the plurality of channels associated with the root channel entry;

deriving a new timestamp value for the channel associated with the root channel entry; and

then repeating the sorting, comparing, and issuing steps.

3. A method of scheduling the transmission of packet cells associated with a plurality of communications channels, comprising the steps of:

sorting channel entries in a heap memory, each channel entry comprising a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, the sorting step identifying a root channel entry corresponding to the next due channel;

comparing the timestamp value of the root channel entry to a global time generated by a reference timer; and

responsive to the comparing step determining that the global time has at least reached the timestamp value of the root channel entry, issuing a transmit credit for the channel associated with the root channel entry;

after the step of issuing a transmit credit, retrieving an allowed cell rate value from a parameter memory for the channel associated with the root channel entry;

deriving a new timestamp value for the channel associated with the root channel entry, the deriving step comprising;

generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value;

adding the offset timestamp value to a base timestamp value to produce the new timestamp value; and

after the deriving step, repeating the sorting, comparing, and issuing steps.

4. The method of claim 3, wherein the base timestamp value equals the timestamp value of the root channel entry.

5. The method of claim 3, wherein the base timestamp value equals the global time.

7. A method of scheduling the transmission of packet cells associated with a plurality of communications channels, comprising the steps of:

sorting channel entries in a heap memory, the sorting step performed by circuitry in a scheduler integrated circuit, each channel entry comprising a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, the sorting step identifying a root channel entry corresponding to the next due channel, and the sorting step comprising;

identifying first and second groups of the plurality of channels, the first group of the plurality of channels having timestamp values that are nearer due than the timestamp values of the second group of the plurality of channels;

storing channel entries for the first group of the plurality of channels in a first parameter memory implemented in the scheduler integrated circuit; and

storing channel entries for the second group of the plurality of channels in a second parameter memory implemented into memory external to the scheduler integrated circuit;

comparing the timestamp value of the root channel entry to a global time generated by a reference timer; and

responsive to the comparing step determining that the global time has at least reached the timestamp value of the root channel entry, issuing a transmit credit for the channel associated with the root channel entry.

9. A method of scheduling the transmission of packet cells associated with a plurality of communications channels, comprising the steps of:

sorting channel entries in a heap memory, each channel entry comprising a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, the sorting step identifying a root channel entry corresponding to the next due channel;

comparing the timestamp value of the root channel entry to a global time generated by a reference timer; and

responsive to the comparing step determining that the global time has at least reached the timestamp value of the root channel entry, issuing a transmit credit for the channel associated with the root channel entry;

after the step of issuing a transmit credit, retrieving an allowed cell rate value for the one of the plurality of channels associated with the root channel entry;

deriving a new timestamp value for the channel associated with the root channel entry, the deriving step comprising;

generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value;

adding the timestamp value for the channel associated with the root channel entry to the offset timestamp value to derive a future credit time value;

comparing the future credit time value with the global time;

responsive to the comparing step determining that the future credit time value is later than the global time, setting the new timestamp value to the future credit time value; and

responsive to the comparing step determining that the future credit time value is earlier than the global time, adding the offset timestamp value to the global time to generate the new timestamp value; and

after the deriving step, repeating the sorting, comparing, and issuing steps.

10. A network hub and ATM translator system, comprising:

a host controller, having an interface for receiving local communications; and

an ATM translator subsystem, comprising;

a transceiver interface, coupled to a high data rate communications facility;

segmentation and reassembly circuitry, coupled to the transceiver interface and to the host controller;

parameter memory, for storing entries associated with each of a plurality of ATM communications channels; and

a scheduler, coupled to the parameter memory and to the segmentation and reassembly processor, for scheduling the transmission of packet cells associated with the plurality of ATM communications channels by a sequence of operations, the scheduler comprising;

heap sort circuitry for sorting channel entries in the parameter memory, each channel entry comprising a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, and for identifying a root channel entry corresponding to the next due channel;

a reference timer for generating a global time;

a comparator for comparing the timestamp value of the root channel entry to the global time; and

source behavior processor circuitry, coupled to the segmentation and reassembly circuitry issuing a transmit credit for the channel associated with the root channel entry.

11. The system of claim 10, wherein the scheduler is integrated into a single integrated circuit.

12. The system of claim 11, wherein the scheduler further comprises:

on-chip parameter memory implemented into the same integrated circuit with the scheduler, for storing timestamp values associated with a first group of the plurality of channels;

wherein the parameter memory is external to the scheduler integrated circuit, and is for storing timestamp values associated with a second group of the plurality of channels, the first group of the plurality of channels having timestamp values that are nearer due than the timestamp values of the second group of the plurality of channels.

13. The system of claim 10, wherein the source behavior processor circuitry is also for retrieving an allowed cell rate value from a parameter memory for the channel associated with the root channel entry after issuing a transmit credit

and wherein the scheduler further comprises:

circuitry, coupled to the heap sort circuitry, for deriving a new timestamp value for the channel associated with the root channel entry.

14. The system of claim 10, wherein the deriving circuitry comprises:

a divider for generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value; and

an adder for adding the offset timestamp value to a base timestamp value to produce the new timestamp value.

15. The system of claim 14, wherein the base timestamp value equals the timestamp value of the root channel entry.

16. The system of claim 14, wherein the deriving circuitry further comprises:

a multiplexer, having a first input for receiving the global time from the reference timer, having a second input for receiving the timestamp value of the root channel entry, having an output coupled to the adder to communicate the base timestamp value thereto, and having a control input for selecting either the global time or the timestamp value of the root channel entry for the base timestamp value; and

a multiplexer control function, for generating a select signal applied to the control input of the multiplexer, by performing the operations of;

generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value;

adding the timestamp value for the channel associated with the root channel entry to the offset timestamp value to derive a future credit time value;

comparing the future credit time value with the global time; and

responsive to the comparing step determining that the future credit time value is later than the global time, setting the new timestamp value to the future credit time value; and

responsive to the comparing step determining that the future credit time value is earlier than the global time, adding the offset timestamp value to the global time to generate the new timestamp value.