System and method for minimizing clock cycles lost to overhead data in a video decoder

• US 6,205,250 B1
• Filed: 08/27/1998
• Issued: 03/20/2001
• Est. Priority Date: 08/27/1998
• Status: Expired due to Term

• Current Assignee: Thomson Licensing SA (Vantiva SA)
• Original Assignee: Thomson Licensing SA (Vantiva SA)
• Inventors: Kranawetter, Greg Alan
• Primary Examiner(s): Couso, Jose L.
• Assistant Examiner(s): Dang, Duy M.
• Application Number:
  US09/140,993
• Time in Patent Office: 936 Days
• Field of Search: 382/232-235, 382/236, 382/238, 382/251, 382/239, 382/241, 382/242, 382/247, 382/248, 370/216, 370/16, 370/338, 348/384.1, 348/390.1, 348/393.1, 348/394.1, 348/420.1
• US Class Current: 382/232
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A video processing device capable of minimizing clock cycles lost to overhead information includes an encoder for generating first and second groups of overhead bits. The first group includes a fixed number of overhead bits and the second group includes a variable number of overhead bits. A shift register receives pixel data from a data source, receives the second group of overhead bits from the encoder, and provides output of the pixel data and the second group of overhead bits. A multiplexer receives the pixel data and the second group of overhead bits from the shift register, receives the first group of overhead bits from the encoder, and provides output of the pixel data and the first and second groups of overhead bits which are then combined in an output register.

Claims

1. In a video processing device, circuitry comprising:

an encoder for generating first and second groups of overhead bits, the first group comprising a fixed number of overhead bits and the second group comprising a variable number of overhead bits, said overhead bits comprising data representing (a) a difference between maximum and minimum pixel values within a block of pixels, (b) a minimum pixel value within the block of pixels, and (c) a difference between the minimum pixel value and a first pixel value within the block of pixels;

a shift register for receiving pixel data from a data source, receiving the second group of overhead bits from the encoder, and providing output of the pixel data and the second group of overhead bits; and

a multiplexer for receiving the pixel data and the second group of overhead bits from the shift register, receiving the first group of overhead bits from the encoder, and providing output of the pixel data and the first and second groups of overhead bits.

2. The circuitry of claim 1, further comprising an output register for receiving the pixel data and the first and second groups of overhead bits from the multiplexer.

3. The circuitry of claim 1, wherein the multiplexer provides outputs in response to a control signal generated by the encoder.

4. The circuitry of claim 1, wherein the shift register provides outputs whenever eight bits are accummulated therein.

5. The circuitry of claim 1, wherein the data source comprises a look-up table.

6. The circuitry of claim 1, wherein a single pixel represented by the pixel data is processed during a single clock cycle.

7. The circuitry of claim 1, wherein the first group of overhead bits includes eight bits.

8. A method for processing data in a video processing device, comprising the steps of:

generating pixel data;

generating first and second groups of overhead bits, the first group comprising a fixed number of overhead bits and the second group comprising a variable number of overhead bits, said overhead bits comprising data representing (a) a difference between maximum and minimum pixel values within a block of pixels, (b) a minimum pixel value within the block of pixels, and (c) a difference between the minimum pixel value and a first pixel value within the block of pixels;

transmitting the pixel data and the second group of overhead bits to an output register by passing the pixel data and the second group of overhead bits through a shift register; and

transmitting the first group of overhead bits to the output register without passing the first group of overhead bits through the shift register.

9. The method of claim 8, wherein the first group of overhead bits includes eight bits.

10. The method of claim 8, wherein a single pixel represented by the pixel data is processed during a single clock cycle.