Data processor with bit unstuffing instruction set extension

• US 6,205,487 B1
• Filed: 11/06/1998
• Issued: 03/20/2001
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Bahr, Raymond G., Cashman, John D., Ye, Wei, Riley, Paul M., Goyette, Leo
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/186,998
• Time in Patent Office: 865 Days
• Field of Search: 709/230, 709/236
• US Class Current: 709/236
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which chance may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Claims

1. A processor comprising:

a first input receiving data;

a second input receiving a zero unstuffing instruction;

a logic unit coupled to the first input and the second input, the logic unit including activatible zero unstuffing circuitry which is activated upon receipt of the zero unstuffing instruction and which unstuffs the data to produce modified data;

an output coupled to the logic unit, the output outputting the modified data; and

wherein the processor can be reprogrammed to execute one of many different instructions.

2. The processor of claim 1 wherein the logic unit further comprises:

a detecting logic device which detects a first predetermined sequence of bits in the data; and

a removal logic device which removes a second predetermined sequence of bits from the data creating the modified data.

3. The processor of claim 1 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform compression on the data.

4. The processor of claim 1 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform decompression on the data.

5. The processor of claim 1 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform encryption on the data.

6. The processor of claim 1 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform decryption on the data.

7. An apparatus comprising a computer readable medium having a processor recorded thereon, the processor comprising:

a first input receiving data;

a second input receiving a zero unstuffing instruction;

a logic unit coupled to the first input and the second input, the logic unit including activatible zero unstuffing circuitry which is activated upon receipt of the zero unstuffing instruction and which unstuffs the data to produce modified data;

an output coupled to the logic unit, the output outputting the modified data; and

wherein the processor can be reprogrammed to execute one of many different instructions.

8. A method of processing data in a processor comprising the steps of:

receiving input data at a processor, which processor is programmable to execute one of many different instructions;

receiving, separately from the input data, a zero unstuffing instruction at the processor;

coupling the input data to a logic unit within the processor, the logic unit including activatible zero unstuffing circuitry;

activating zero unstuffing circuitry in the logic unit upon the receipt of the zero unstuffing instruction;

unstuffing the data to produce modified data; and

outputting the modified data.

9. The method of claim 8 further comprising:

detecting a first predetermined sequence of bits in the data; and

removing a second predetermined sequence of bits from the data creating the modified data.

10. The method of claim 9 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform compression on the data.

11. The method of claim 9 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform decompression on the data.

12. The method of claim 9 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform encryption on the data.

13. The method of claim 9 wherein the zero unstuffing instruction executes on the logic unit as part of a protocol to perform decryption on the data.