Computer system management apparatus and method

• US 6,205,547 B1
• Filed: 11/20/1998
• Issued: 03/20/2001
• Est. Priority Date: 11/20/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Davis, Edward L.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Patel, Nitin
• Application Number:
  US09/197,384
• Time in Patent Office: 851 Days
• Field of Search: 713/1, 713/2
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16

Abstract

A system management controller may record and/or modify the state of the computer system'"'"'s host processor if it fails to execute user level program instructions (e.g., is hung). The system management controller may also be commanded, from a site remote from the computer system, to acquire and/or modify the state of the host processor. The system management controller may also acquire and/or modify the state of the other components coupled to the computer system such as, for example, a modem, a network interface card, a memory, and a bus-to-bus bridge circuit.

Claims

1. A computer system comprising:

a main computing unit including a host processor, and a host bus coupled to the host processor;

a storage storing an operating system; and

a system management controller coupled to the main computing unit to determine an operational state of the main computing unit when the main computing unit is being controlled by the operating system and, based on the determination, selectively regulate the main computing unit.

2. The computer system of claim 1, wherein determination of the operational state comprises determining a state of the host processor.

3. The computer system of claim 2, wherein the state of the host processor comprises identification of the contents of a register internal to the host processor.

4. The computer system of claim 1, wherein the system management controller is further configured to modify the determined state of the host processor.

5. The computer system of claim 2, wherein determination of the operational state further comprises determination of a state of a bus device coupled to the host bus.

6. The computer system of claim 5, wherein the bus device comprises a bridge circuit.

7. The computer system of claim 5, wherein the bus device comprises a memory.

8. The computer system of claim 5, wherein the system management controller is further configured to modify the determined state of the bus device.

9. The computer system of claim 1, wherein the system management controller comprises:

a management processor;

a management bus coupled to the management processor;

a communication circuit coupled to the management bus and configured to couple to the main computing unit; and

memory coupled to the management bus and including a program executable by the management processor to configure the management processor to interact with the communication circuit to perform the regulation.

10. The computer system of claim 9, wherein the system management controller further comprises a modem interface circuit coupled to the management bus.

11. The computer system of claim 9, wherein the system management controller further comprises a circuit coupled to the management bus and configured to receive input signals indicative of main computing unit state.

12. The computer system of claim 11, wherein the main computing unit state comprises an indication of whether the host processor is executing user application program instructions.

13. The computer system of claim 9, wherein the system management controller further comprises a serial interface circuit coupled to the management bus.

14. The computer system of claim 9, wherein the system management controller further comprises a thermal control circuit coupled to the management bus and configured to receive a signal indicative of a thermal state of the main computing unit.

15. The computer system of claim 14, wherein the thermal control circuit is further configured to transmit a thermal control signal to the main computing unit.

16. The computer system of claim 14, wherein the thermal control signal comprises a signal to modify operation of a fan coupled to the main computing unit.

17. The computer system of claim 1, wherein the system management controller is coupled to the main computing unit by a inter-integrated circuit control bus.

18. The computer system of claim 1 including a housing around said main computing unit, said controller detects when said housing has been opened.

19. The computer system of claim 1 including a fan coupled to said controller, said controller detecting when the temperature exceeds a predetermined threshold and in response operating said fan.

20. The computer system of claim 1 including a power supply having a voltage, said controller determining when the power supply voltage exceeds a threshold and in response altering an operating characteristic of said computing unit in response thereto.

21. A method to manage a computer system having a host processor, a bus coupled to the host processor, and a device coupled to the bus, said computer system being controlled by its own operating system, the method comprising:

receiving a signal indicative of an operating mode of the computer system being controlled by its own operating system; and

determining if the signal indicates the computer system is operating in a normal mode and, if it is not, then regulating the computer system independently of the host processor.

22. The method of claim 21, wherein regulating comprises determining a state of the host processor.

23. The method of claim 22, further comprising modifying the state of the host processor.

24. The method of claim 21, wherein regulating comprises determining a state of the device.

25. The method of claim 24, further comprising modifying the state of the device.

26. The method of claim 21, wherein receiving a signal comprises receiving a signal from the device.

27. The method of claim 26, wherein the device is a communications device, and the signal represents a command signal.

28. The method of claim 21 including determining whether the housing for said computer system has been opened using a controller coupled to said host processor.

29. The method of claim 21 including determining when a thermal event has occurred using a controller coupled to said host processor and using said controller to control fans to cool said computer system.

30. The method of claim 21 including determining when the power supply voltage has exceeded a threshold and in response thereto using a controller coupled to said host processor to alter the operating characteristics of said host processor.

31. A program storage device, readable by a processor-based system, comprising:

instructions stored thereon for causing the processor-based system to;

receive a signal indicative of an operating mode of a computer system being controlled by its own operating system; and

determine if the signal indicates the computer system is operating in a normal mode and, if it is not, then regulate the computer system independently of a host processor of the computer system.

32. The program storage device of claim 31, wherein the instructions to regulate comprise instructions to determine a state of the host processor.

33. The program storage device of claim 32, wherein the instructions to regulate further comprise instructions to modify the state of the host processor.