Semiconductor integrated circuit device comprising a memory array and a processing circuit

• US 6,205,556 B1
• Filed: 11/24/1998
• Issued: 03/20/2001
• Est. Priority Date: 01/24/1990
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kimura, Katsutaka, Watanabe, Takao, Kawajiri, Yoshiki, Itoh, Kiyoo
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/198,658
• Time in Patent Office: 847 Days
• Field of Search: 712/28, 712/35, 712/39, 712/40, 712/4, 710/260, 713/310, 713/330
• US Class Current: 713/330
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

Claims

1. A semiconductor integrated circuit device, comprising:

a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at points of intersection thereof;

a control circuit coupled to said memory array via a plurality of first signal lines;

a processing circuit coupled to said control circuit via a plurality of second signal lines;

an input/output circuit coupled to said control circuit via a third signal line, and

a control node to which a control signal is input,

wherein the semiconductor integrated circuit device is formed on a chip,

wherein said control circuit has a switching circuit for selectively connecting one of the first signal lines to the third signal line,

wherein the control signal is supplied from outside of the chip, and

wherein said processing circuit can be disabled based on the control signal.

2. A semiconductor integrated circuit device according to claim 1,

wherein the plurality of first signal lines are coupled to the plurality of bit lines for transmitting first data read from a subset of the plurality of memory cells.

3. A semiconductor integrated circuit device according to claim 2,

wherein the switching circuit transfers selected ones of the first data to the third signal line.

4. A semiconductor integrated circuit device according to claim 3,

wherein said input/output circuit has a first node for outputting a read datum outside of the chip, the read datum being the selected ones of the first data.

5. A semiconductor integrated circuit device according to claim 4,

wherein said input/output circuit has a second node for inputting a write datum from the outside of the chip,

wherein the second node is coupled to said control circuit via a fourth signal line,

wherein said control circuit transfers the write datum to one of the plurality of first signal lines.

6. A semiconductor integrated circuit device according to claim 4

wherein when the switching circuit connects one of the first signal lines to the third signal line, said processing circuit is disabled.

7. A semiconductor integrated circuit device according to claim 4, wherein said processing circuit includes an arithmetic circuit.

8. A semiconductor integrated circuit device according to claim 1,

wherein the plurality of first signal lines are coupled to the plurality of bit lines and transmit first data read from a subset of the plurality of memory cells,

wherein mid control circuit transfers the first data to the plurality of second signal lines,

wherein said processing circuit is coupled to said input/output circuit via a processed signal line,

wherein said processing circuit outputs a processed datum on the processed signal line, the processed datum being the processed result of the first data.

9. A semiconductor integrated circuit device according to claim 8,

wherein when the switching circuit connects one of the first signal lines to the third signal line, said processing circuit is disabled.

10. A semiconductor integrated circuit device according to claim 8, wherein said processing circuit includes an arithmetic circuit.

11. A semiconductor integrated circuit device according to claim 1,

wherein when the switching circuit connects one of the first signal lines to the third signal line, said processing circuit is disabled.

12. A semiconductor integrated circuit device according to claim 1, wherein said processing circuit includes an arithmetic circuit.

13. A semiconductor integrated circuit device according to claim 1,

wherein said processing circuit has a plurality of processing units, and

wherein the plurality of processing units operate in parallel.

14. A semiconductor integrated circuit device formed on a single chip, comprising:

a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at points of intersection thereof;

a control circuit coupled to said memory array via a plurality of first signal lines;

a processing circuit coupled to said control circuit via a plurality of second signal lines;

an input/output circuit coupled to said control circuit via a third signal line, and

a control node coupled to said processing circuit to which a control signal is supplied from outside the chip,

wherein said control circuit has a switching circuit for selectively connecting one of the first signal lines to the third signal in order to disable the processing circuit.

15. A semiconductor integrated circuit device according to claim 14,

wherein the plurality of first signal lines are coupled to the plurality of bit lines for transmitting first data read from a subset of the plurality of memory cells.

16. A semiconductor integrated circuit device according to claim 15,

wherein the switching circuit transfers selected ones of the first data to the third signal line.

17. A semiconductor integrated circuit device according to claim 16,

wherein said input/output circuit has a first node for outputting a read datum outside of the chip, the read datum being the selected ones of the first data.

18. A semiconductor integrated circuit device according to claim 17,

wherein said input/output circuit has a second node for inputting a write datum from the outside of the chip,

wherein the second node is coupled to said control circuit via a fourth signal line,

wherein said control circuit transfers the write datum to one of the plurality of first signal lines.

20. A semiconductor integrated circuit device according to claim 14,

wherein said processing circuit has a plurality of processing units which operate in parallel.

21. A semiconductor integrated circuit device according to claim 18,

wherein said processing circuit has a plurality of processing units which operate in parallel.

19. A semiconductor integrated circuit device according to clam 18, wherein said processing circuit includes an arithmetic circuit.