Delay analysis result display device

• US 6,205,573 B1
• Filed: 10/21/1998
• Issued: 03/20/2001
• Est. Priority Date: 10/22/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hasegawa, Takumi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/176,426
• Time in Patent Office: 881 Days
• Field of Search: 716/1-21
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A delay analysis result of a designated path in a logic circuit is stored in a delay analysis result storage means 41, element and wire information of the overall logic circuit is stored in the circuit storage means 42, and information for designating a wire in a designated path to be the root of extension of analysis is stored in designator storing means 43. Display means 44 picks up from circuit storage means 42 wires and elements which are connected to the designated wire and are not contained in the designated path, and displays them together with the designated path which is an analysis target in delay analysis result storage means 41.

Claims

1. A delay analysis result display device which displays a delay time analysis result of each of electrical signals in a designated path in an electrical circuit, which comprises:

a delay time analysis result storage device that stores said delay time analysis result;

a circuit information storage device that stores circuit information containing the delay time of each of electrical signals of all paths in said electrical circuit;

a designator storage device that designates a wire between any elements in said designated path; and

a display device that displays said delay time analysis result while adding into said designated path other wires which are not contained in said designated path, but contained in said electrical circuit and which are electrically coupled to said designated wire, and displays the delay time analysis result of each of electrical signals of said other wires.

2. The delay analysis result display device as set forth in claim 1, wherein said display device displays said delay time analysis result while adding other elements and further wires which are electrically coupled to said other wires.

3. The delay analysis result display device as set forth in claim 1, wherein said designated path is a path which extends from one flip-flop to another flip-flop through wires and elements between said two flip-flops.

4. The delay analysis result display device as set forth in claim 1, wherein said delay time analysis result of said each of electrical signals in said designated path contains at least the name of each element contained in said designated path, the delay time of said each element, the name of each wire contained in said designated path and the delay time of said each wire.

5. The delay analysis result display device as set forth in claim 1, wherein said circuit information containing the delay time of each of the electrical signals of all the paths in said electrical circuit contains at least the name of each of elements contained in all the paths, the delay time of each of said elements contained in all the paths, the name of each of wires contained in all the paths, and the delay time of each of said wires contained in all the paths.

6. The delay analysis result display device as set forth in claim 1, wherein said display device at least displays elements in said designated path and wires between said elements in said designated path, and said designator storage device stores any wire selected from the wires displayed on said display device.

7. The delay analysis result display device as set forth in claim 1, wherein said electrical circuit is a logic circuit.

8. A system for displaying a delay analysis result, comprising:

a first memory device that stores information for a circuit;

a second memory device that stores results of said delay analysis for said circuit;

a third memory device that stores information for a designated path of said circuit; and

a display device that generates a display in accordance with a delay analysis result for said designated path and adds display information to said display for a non-designated path, wherein said non-designated path is coupled to said designated path.

9. The system of claim 8, wherein said circuit information comprises information on elements and wires for said circuit.

10. The system of claim 9, wherein said circuit comprises an integrated circuit.

11. The system of claim 9, said elements and wires respectively comprising nodes and arcs.

12. The system of claim 8, wherein said second memory device comprises a first table that stores overall path information and a second table that stores individual path information.

13. The system of claim 8, wherein said delay analysis results comprise delay times for a portion of said designated path.

14. The system of claim 8, wherein said designated path information comprises a reference indicator, a designation of a target as one of a wire and an element, and a location indicator for said target.

15. The system of claim 8, further comprising a pointing device that obtains said designated path information.

16. The system of claim 8, wherein said display device comprises a visual display.

17. The system of claim 8, wherein said circuit is a logic circuit.

18. The system of claim 8, wherein said designated path comprises a path extending from a first flip-flop to a second logic flip-flop via wires and elements coupled between said first flip-flop and said second logic flip-flop.

19. A method for displaying results of a delay analysis, comprising:

receiving and storing electrical circuit data stored in a memory device;

designating a path in said electrical circuit and storing designation information in said memory device;

displaying a result for said designated path in accordance with said delay analysis and said designation information; and

displaying a non-displayed portion for other wires not contained in said designated path, wherein other wires are displayed with said displayed result for said designated path.

20. The method of claim 19, further comprising terminating said method when said designation information is not present in said memory device.

21. The method of claim 20, said displaying said non-displayed portion step comprising the step of displaying a previously non-displayed portion for a first wire not contained in said designated path, elements coupled to said previously non-displayed portion, and wires coupled to said elements.

22. The method of claim 21, further comprising deleting said designation information from said memory device.

23. The method of claim 19, further comprising displaying delay time data for said designated path.

24. The method of claim 19, further comprising differentiating said designated path and said other wires by a first display scheme and a second display scheme.

25. The method of claim 19, wherein said display steps comprise graphically representing said designated path and said other wires in a video device.