Low temperature thin film transistor fabrication

• US 6,207,472 B1
• Filed: 03/09/1999
• Issued: 03/27/2001
• Est. Priority Date: 03/09/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Purushothaman, Sampath, Callegari, Alessandro Cesare, Dimitrakopoulos, Christos Dimitrios
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US09/265,161
• Time in Patent Office: 749 Days
• Field of Search: 438/99, 438/149, 438/216, 438/287, 438/158, 438/240, 438/785
• US Class Current: 438/99
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/472 the gate dielectric comprising only inorganic materials
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Abstract

The invention broadens the range of materials and processes that are available for Thin Film Transistor (TFT) devices by providing in the device structure an organic semiconductor layer that is in contact with an inorganic mixed oxide gate insulator involving room temperature processing at up to 150 degrees C.

A TFT of the invention has a pentacene semiconductor layer in contact with a barium zirconate titanate gate oxide layer formed on a polycarbonate transparent substrate employing at least one of the techniques of sputtering, evaporation and laser ablation.

Claims

1. In a process of fabricating a low temperature thin film transistor by serial deposition of at least a semiconductor layer in contact with a gate insulation layer, the improvement comprising in combination:

providing a substrate of at least one material talen from the group of polycarbonate, polyethylene terephthalate, silicon, quartz and glass,

depositing , by a process taken from the group of sputtering, spinning, evaporation and laser ablation at a substrate temperature in the range of about 25 to 150 degrees C.,

a gate electrode on said substrate,

said gate electrode being taken from the group of doped silicon, gold, silver, copper, aluminum, molybdenum, platinum and conducting polymers,

an inorganic oxide gate insulation layer on said substrate and over said gate,

said gate insulation being of at least one inorganic oxide taken from the group of inorganic oxides including Ta₂O₃, V₂O₃, Ti O₂, the ferroelectric insulators Bi₄Ti₃O₁₂, Ba Mg F₄, Sr Ti O₃, and the mixed oxides Sr Bi₂Ta(_1-x)Nb(_x)O₃, PbZr(_x)Ti(_1-x)O₃, BaZr(_x)Ti(_1-x)O₃, and Ba(_x)Sr(_1-x)TiO₃,

an organic semiconductor layer over said inorganic oxide gate insulation layer and,

source and drain electrodes on said organic semiconductor layer overlapping said gate and separated by a channel distance,

said source and drain electrodes being taken from the group of doped silicon, gold, silver, copper, aluminum, molybdenum, platinum and conducting polymers.

2. The process of claim 1 wherein said organic semiconductor layer is of the material pentacene.

3. The process of fabricating a low temperature thin film transistor through serial deposition of layers on a substrate, comprising in combination the steps of:

performing said deposition of layers in a temperature range of about 25 to 150 degrees C., and during said deposition,

employing at least one room temperature deposition process taken from the group of sputter spinning, evaporation and laser ablation, and serially,

depositing a gate electrode on said substrate,

depositing an inorganic oxide gate insulation layer on said substrate and over said gate electrode, and,

depositing an organic semiconductor layer on said gate insulation layer including a step of depositing source and drain electrodes separated by a channel distance.

4. The process of claim 3 wherein the step of depositing said source and drain electrodes occurs before said step of depositing said organic semiconducting layer.

5. The process of claim 3 wherein the step of depositing said source and drain electrodes occurs after said step of depositing said organic semiconducting layer.

6. The process of claim 3 wherein said room temperature deposition process is sputtering.

7. The process of claim 6 wherein said organic semiconductor is pentacene.

8. The process of claim 7 wherein said gate oxide layer is barium zirconate titanate.

9. The process of claim 8 wherein said gate electrode and said source and drain electrodes are of silicon doped to 0.003 ohm cm.

10. The process of claim 9 wherein said substrate is a layer of polycarbonate plastic.