Method for forming a tantalum oxide capacitor using two-step rapid thermal nitridation

• US 6,207,488 B1
• Filed: 10/22/1998
• Issued: 03/27/2001
• Est. Priority Date: 10/22/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Ki-hyun, Park, Jae-young, Byun, Jae-ho
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US09/177,841
• Time in Patent Office: 887 Days
• Field of Search: 438/238, 438/239, 438/240, 438/397, 438/398, 438/393, 438/235, 438/3, 438/964
• US Class Current: 438/240
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02326 into a nitride layer, e.g. changing SiN to SiON
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3211 Nitridation of silicon-containing layers
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A method for forming a Ta₂O₅ capacitor on a semiconductor device reduces leakage current and increases cell capacitance by utilizing a two-step rapid thermal nitridation (RTN) process to form a nitride layer on a hemi-spherical grain (HSG) storage node. The first RTN process is performed in a NH₃ atmosphere at 800±40° C. for 180±60 seconds, thereby forming a nitride layer having a thickness of about 4 Å. The second RTN process is performed in a NH₃ atmosphere at 850±40° C. for 180±60 seconds, thereby increasing the thickness of the nitride layer to at least about 7 Å. Therefore, a nitride layer that is thick enough to act as an oxidation barrier is achieved, but agglomeration of the HSGs on the storage node due to high process temperatures is prevented. To make the structure more readily adaptable to process for manufacturing DRAMs with Ta₂O₅ dielectric layers, a rapid thermal oxidation (RTO) process can then be performed in an O₂ or N₂O atmosphere at 850±50° C. for 90±30 seconds to thereby form a combined layer comprising a nitride layer and an oxide layer.

Claims

1. A method for forming a capacitor having a tantalum oxide dielectric layer comprising:

a) forming a capacitor storage node on a semiconductor substrate;

b) performing a first rapid thermal nitridation (RTN) process on the semiconductor substrate at a first temperature that does not change the electrical characteristics of the storage node, thereby forming a nitride layer;

c) performing a second RTN process on the semiconductor substrate at a second temperature, thereby making the nitride layer thicker; and

d) depositing a tantalum oxide dielectric layer over the nitride layer.

2. The method of claim 1, wherein step a) includes forming a storage node having a surface with hemispherical grains.

3. The method of claim 1, further including cleaning the semiconductor substrate after forming the storage node.

4. The method of claim 1, wherein the first temperature is 800±

40°

C.

5. The method of claim 1, wherein the first RTN process is performed for 180±

60 sec.

6. The method of claim 1, wherein the second temperature is 850±

40°

C.

7. The method of claim 1, wherein the second RTN process is performed for 180±

60 sec.

8. The method of claim 1, further including performing a rapid thermal oxidation (RTO) process on the semiconductor substrate after the second RTN process is performed.

9. The method of claim 8, wherein the RTO process is performed at 850+50°

C.

10. The method of claim 8, wherein the RTO process is performed for 90±

30 sec.

11. The method of claim 8, wherein the RTO process is performed in an O₂ or N₂O atmosphere.

12. The method of claim 1, wherein the second temperature is higher than the first temperature.

13. A method for forming a capacitor on a semiconductor substrate comprising:

forming a capacitor storage node on the semiconductor substrate;

forming a nitride layer having a thickness on the storage node through a first rapid thermal nitridation (RTN) process at a first temperature that does not change the electrical characteristics of the storage node;

increasing the thickness of the nitride layer by performing a second RTN process at a second temperature; and

depositing a dielectric layer over the nitride layer.

14. The method of claim 13, wherein the first temperature is 800±

40°

C.

15. The method of claim 13, wherein the first RTN process is performed for 180±

60 sec.

16. The method of claim 13, wherein the second temperature is 850±

40°

C.

17. The method of claim 13, wherein the second RTN process is performed for 180±

60 sec.

18. The method of claim 13, wherein the second temperature is higher than the first temperature.

19. A method for forming a capacitor on a semiconductor substrate comprising:

a step for forming a capacitor storage node on the semiconductor substrate;

a step for forming a nitride layer having a thickness on the storage node;

a step for increasing the thickness of the nitride layer; and

a step for depositing a dielectric layer over the nitride layer.

20. A method according to claim 19, wherein:

the step for forming a nitride layer comprises performing a first RTN process at a first temperature; and

the step for increasing the thickness of the nitride layer comprises performing a second RTN process at a second temperature that is higher than the first temperature.