Method for fabricating a radio frequency power MOSFET device having improved performance characteristics

• US 6,207,508 B1
• Filed: 08/03/1999
• Issued: 03/27/2001
• Est. Priority Date: 08/03/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Patel, Viren C.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/366,246
• Time in Patent Office: 602 Days
• Field of Search: 438/137, 438/138, 438/268, 438/273, 438/532
• US Class Current: 438/268
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance C_gd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Claims

1. Forming a vertical MOSFET device, comprising the steps of:

forming a semiconductor substrate having first and second opposing major surfaces;

growing a first oxide layer on the first surface;

depositing polysilicon on the first oxide layer;

defining a polysilicon layer from the polysilicon;

forming a body region of second conductivity type extending into the substrate and under the polysilicon layer from the first surface and defining a drain region having an extended drain portion bounded by the body region;

forming a source region of first conductivity type extending into the substrate from the first surface within the boundaries of the body region;

forming a channel portion, defined at the first surface by the source region and the extended drain portion, wherein the polysilicon layer overlays a portion of the source region, the channel portion, and at least a portion of the extended drain portion adjacent the channel portion;

forming a drain electrode contacting the drain region on the second surface;

selectively doping the polysilicon layer to form a polysilicon gate electrode disposed on the first surface over the channel portion and at least a portion of the extended drain portion adjacent the channel portion and an undoped polysilicon region disposed on the first surface adjacent to the polysilicon gate electrode over a substantial portion of the extended drain portion;

growing a second oxide layer disposed over the polysilicon gate electrode and the undoped polysilicon region;

forming a first window in the second oxide layer over the polysilicon gate electrode so as to expose a top surface of the polysilicon gate electrode, wherein a portion of the second oxide layer that overlays the undoped polysilicon region is not effected by forming the first window; and

placing a layer of metal in the first window in the second oxide layer over the polysilicon gate electrode and over the second oxide layer to form a metal gate electrode having electrical contact with the polysilicon gate electrode, wherein the portion of second oxide layer over the undoped polysilicon region protects the undoped polysilicon region from the layer of metal.

2. The method of claim 1, wherein after the step of growing the second oxide layer and prior to the step of placing the layer of metal, comprising the additional steps of:

forming a second window in the second oxide layer over the source region so as to expose the source region; and

simultaneous with forming the metal gate electrode, placing the metal layer in the second window in the second oxide layer to form a source electrode contacting the source region.

3. A method for forming a vertical MOSFET device, comprising the steps of:

forming a semiconductor substrate having first and second opposing major surfaces;

growing a first oxide layer on the first surface;

depositing polysilicon on the first oxide layer;

defining a polysilicon layer from the polysilicon;

forming a pair of body regions of second conductivity type extending into the substrate and under the polysilicon layer from the first surface and defining a drain region having an extended drain portion bounded by the pair of body regions;

forming a pair of source regions of first conductivity type, each extending into the substrate from the first surface within the boundaries of a body region of the pair of body regions;

forming a pair of channel portions, defined at the first surface by the pair of source regions and the extended drain portion therebetween, wherein the polysilicon layer overlays a portion of the pair of source regions, the pair of channel portions, and at least a portion of the extended drain portion adjacent the pair of channel portions;

forming a drain electrode contacting the drain region on the second surface;

selectively doping the polysilicon layer to form a pair of polysilicon gate electrodes disposed on the first surface over the pair of channel portions and at least a portion of the extended drain portion adjacent the pair of channel portions and an undoped polysilicon region disposed on the first surface adjacent to the pair of polysilicon gate electrodes over a substantial portion of the extended drain portion;

growing a second oxide layer disposed over the pair of polysilicon gate electrodes and the undoped polysilicon region;

forming first and second windows in the second oxide layer over the pair of polysilicon gate electrodes so as to expose a top surface of the pair of polysilicon gate electrodes, wherein a portion of the second oxide layer that overlays the undoped polysilicon region is not effected by forming the first and second windows; and

placing a layer of metal in the first and second windows in the second oxide layer over the pair of polysilicon gate electrodes and over the second oxide layer to form a pair of metal gate electrodes having electrical contact with the polysilicon gate electrode, wherein the portion of second oxide layer over the undoped polysilicon region protects the undoped polysilicon region from the layer of metal.

4. The method of claim 3, wherein after the step of growing the second oxide layer and prior to the step of placing the layer of metal, comprising the additional steps of:

forming third and fourth windows in the second oxide layer over the pair of source regions so as to expose the pair of source regions; and

simultaneous with forming the pair of metal gate electrodes, placing the metal layer in the third and fourth windows in the second oxide layer to form a pair of source electrodes contacting the pair of source regions.