Memory cell with a stacked capacitor

• US 6,207,524 B1
• Filed: 09/29/1998
• Issued: 03/27/2001
• Est. Priority Date: 09/29/1998
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Gutsche, Martin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/162,867
• Time in Patent Office: 910 Days
• Field of Search: 438/396, 438/239, 438/253, 438/381, 438/238, 438/240, 438/395, 437/47, 437/52, 437/60, 437/238, 437/919
• US Class Current: 438/396
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A semiconductor memory cell includes a field effect transistor coupled to a storage capacitor that formed as a multilayer stack over the surface of the silicon chip of the cell. The capacitor is formed by three conformal layers over the surface of a cup-shaped contact hole in a silicon oxide layer overlying the surface of the chip.

Claims

1. A method for forming a memory cell including a transistor and a capacitor comprising the steps of:

forming in a semiconductor chip a transistor having first and second regions of one conductivity-type spaced apart by a region of the opposite conductivity-type along a top surface of the chip;

forming a dielectric layer over a top surface of the chip;

forming a contact hole with substantially vertical side walls in the dielectric layer by anisotropic etching for exposing a top surface portion of the second region of the transistor;

filling the contact hole with a conductive fill for providing a low resistance connection to the second region;

removing the top portion of the conductive fill of the contact hole for forming a recess in the conductive fill and exposing the dielectric layer in the contact hole;

etching the exposed dielectric layer isotropically for widening the recess and enlarging the surface area of the contact hole in the dielectric layer;

depositing a first conductive layer conformally over the enlarged surface area of the contact hole suitable for use as a lower plate of a storage capacitor;

patterning the first conductive layer to confine the first conductive layer to the interior of the contact hole by etching a portion of the first conductive layer with etchants introduced at an acute angle relative to the top surface;

depositing a layer of a material of high dielectric constant for covering over the first conductive layer; and

depositing s second conductive layer conformally over the last dielectric layer suitable for use as an upper plate of a capacitor that comprises the electrically isolated upper and lower plates separated by the layer of high dielectric constant.

2. The method of claim 1 in which the conductive material used to fill the contact hole is doped polysilicon and that of the first and second conductive layers is of a metal.

3. The method of claim 2 in which the metal is platinum for both the first and second conductive layers.

4. The method of claim 3 in which a conductive diffusion barrier layer is deposited between the doped polysilicon and the first platinum layer.

5. The method of claim 4 in which the conductive diffusion barrier layer is of a material chosen from the group consisting of TiN, TaSiN, and TiNAl.

6. The method of claim 4 in which the material of high dielectric constant is barium strontium titanate.

7. The method of claim 1 in which the patterning includes the step of ion-beam etching an upper portion of the first conductive layer.

8. The method of claim 1 in which the recess after widening is essentially cup-shaped.

9. The method of claim 1 wherein the first dielectric layer is largely silicon dioxide.

14. The method of claim 1 wherein the step of etching the exposed dielectric layer includes widening the recess to form a cup-shaped recess which gradually narrows from a top portion to the contact hole with the conductive fill.

10. A method of forming a stacked capacitor on the top surface of a silicon wafer for use as a storage capacitor in series with a switching transistor formed in a top surface portion of the silicon wafer comprising the steps of:

forming a first dielectric layer over the top surface of the silicon wafer;

forming a contact hole in the dielectric coating for exposing the portion of the silicon transistor to which the lower plate of the storage capacitor is to be electrically connected;

partially filling the contact hole with doped polysilicon suitable for forming an electrical connection to said portion of the silicon transistor;

widening the unfilled portion of the contact hole to essentially a cup-shape for enlarging the surface area of the unfilled portion;

forming a diffusion barrier conductive layer over the doped polysilicon;

depositing conformally over the surface of the unfilled portion of the contact hole, a first conductive layer suitable for serving as said lower plate of the capacitor;

ion etching to remove an upper portion of the first conductive layer in the contact hole;

depositing conformally over the first conductive layer and the contact hole a second dielectric layer suitable for serving as the dielectric of the capacitor; and

depositing conformally over the second dielectric layer a second conductive layer suitable for serving as the upper plate of the capacitor without providing an electrical short to the lower plate of the capacitor.

11. The method of claim 10 in which the second dielectric layer and the second conductive layer extend over the top surface of the silicon wafer for serving other stacked capacitors in the silicon wafer.

12. The method of claim 11 in which the contact hole when first formed in the first dielectric layer has vertical side walls and is formed by anisotropic reactive ion etching and the contact hole is later widened essentially to a cup-shape by isotropic etching.

13. The method of claim 12 in which the first dielectric layer is largely silicon dioxide, the first and second conductive layers are of platinum, and the dielectric of the capacitor is of barium strontium titanate, and the diffusion barrier conductive layer is chosen from a group consisting of TiN, TaSiN, and TiNAl.

15. The method of claim 10, wherein the step of widening includes widening the recess to form a cup-shaped recess which gradually narrows from a top portion to the contact hole with the conductive fill.