Method for fabricating a micromachined chip scale package

• US 6,207,548 B1
• Filed: 03/05/1997
• Issued: 03/27/2001
• Est. Priority Date: 03/07/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Hembree, David R., Akram, Salman
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US08/811,711
• Time in Patent Office: 1,483 Days
• Field of Search: 438/611, 438/612, 438/613, 438/125, 438/614, 438/615, 438/118, 438/106, 438/108, 257/777, 257/778, 257/737, 298/40, 228/180.22
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Claims

1. A method of rerouting bond pads of at least one semiconductor die, comprising:

providing at least one semiconductor die of a selected size having a first plurality of bond pads respectively positioned at a first pluraity of positions;

providing a discrete preformed blank size not to exceed the size of the at least one semiconductor die;

forming a second plurality of bond pads respectively positioned at a second plurality of positions differing from the first plurality of positions of the first plurality of bond pads and forming circuit traces to extend between the first plurality of bond pads of the at least one semiconductor die and the second plurality of bond pads;

forming apertures in the discrete preformed blank corresponding with the second plurality of positions of the second plurality of bond pads; and

assembling the discrete preformed blank to the at least one semiconductor die with the circuit traces extending between and in communication with the first plurality of bond pads. the second plurality of bond pads, and the apertures of the discrete preformed blank.

2. The method of claim 1, further including forming the circuit traces to extend at least partially between the discrete preformed blank and the at least one semiconductor die.

3. The method of claim 1, further including forming the circuit traces to extend at least partially on a surface of the discrete preformed blank which remains exposed after the discrete preformed blank and the at least one semiconductor die are assembled.

4. The method of claim 1, wherein the at least one semiconductor die comprises a plurality of semiconductor dies integral with a wafer.

5. The method of claim 1, further comprising forming the at least one semiconductor die of a semiconductor material and forming the provided discrete preformed blank of the same semiconductor material as the at least one semiconductor die.

6. The method of claim 1, further comprising:

fabricating an integrated circuit including external electrical connections on an active surface of the at least one semiconductor die.

7. The method of claim 1, further comprising:

providing a die-attach material; and

bonding the discrete preformed blank with the die-attach material to an active suuface of the at least one semiconductor die.

8. The method of claim 1, further including bonding the discrete preformed blank to at least one semiconductor die to form a substantially hermetic seal.

9. The method of claim 8, further including passivating an active surface of the at least one semiconductor die before bonding the discrete preformed blank to the at least one semiconductor die.

10. The method of claim 8, further including passivating the exerior of the at least one semiconductor die and the discrete preformed blank after bonding the discrete preformed blank to an active surface of the at least one semiconductor die.

11. The method of claim 8, further comprising simultaneously bonding the discrete preformed blank and the at least one semiconductor die in combination with a plurality of other semiconductor dies and a plurality of other discrete preformed blanks.

12. The method of claim 11, wherein, during bonding, all of the semiconductor dies remain unsevered from a wafer, and all of the discrete preformed blanks remain unsevered from a discrete preformed blank having selected surface dimensions not in excess of surface dimensions of the wafer.

13. The method of claim 12, further comprising burning-in and testing all of the semiconductor dies included in the bonding of the wafer and the wafer-sized discrete preformed blank prior to severing the semiconductor dies therefrom.

14. The method of claim 12, further comprising severing at least some of the semiconductor dies with discrete preformed blanks having preselected surface dimensions not in excess of surface dimensions of the active surface of the severed semiconductor dies from the bonded wafer and discrete preformed blank after burning-in and testing.

15. The method of claim 14, further including singulating the semiconductor dies with attached die-size discrete preformed blanks from the bonded wafer and wafer-size discrete preformed blank.

16. The method of claim 1, further comprising disposing a conductive material in at least one of the of apertures of the discrete preformed blank.

17. A method of claim 1, wherein forming the second plurality of bond pads comprises forming at least one of the second plurality of bond pads on a face of the discrete preformed blank.

18. The method of claim 1, wherein forming the second plurality of bond pads comprises forming the second plurality of bond pads on a back side of the discrete preformed blank.

19. The method of claim 18, wherein forming apertures in the discrete preformed blank comprises micromaching the apertures in a front face of the discrete preformed blank.

20. The method of claim 18, wherein forming the second plurality of bond pads and forming the circuit traces on the back side of the discrete preformed blank comprises applying a conductor-carrying dielectric film to at least a portion of the back side of the discrete preformed blank.

21. The method of claim 1, wherein forming the second plurality of bond pads at a second plurality of positions comprises locating the second plurality of positions generally along a selected common edge of the at least one semiconductor die and the discrete preformed blank.

22. The method of claim 21, further comprising forming a plurality of mutually parallel trenches extending generally perpendicularly from the selected common edge of the at least one semiconductor die and the discrete preformed blank and being communicative with the apertures of the discrete preformed blank.

23. A method of rerouting bond pads of semiconductor dice, comprising:

providing a wafer of a selected size having a plurality of semiconductor dice, at least some of the plurality of semiconductor dies each having an active surface having a first plurality of bond pads respectively positioned at a first plurality of positions;

providing a wafer-size discrete preformed blank size not to exceed the size of the wafer;

forming a second plurality of bond pads respectively positioned at a second plurality of positions differing from the first plurality of positions of the first plurality of bond pads and forming circuit traces to extend between the first plurality of bond pads of the at least some of the plurality of semiconductor dies and the second plurality of bond pads;

forming apertures in the wafer-size discrete preformed blank corresponding with the second plurality of positions of the second plurality of bond pads;

passivating at least a portion of the active surfaces of the at least some of the plurality of semiconductor dies; and

assembling the wafer-size discrete preformed blank to the wafer after passivating at least a portion of the active surface of the at least some of the plurality of semiconductor dies with the circuit traces extending between and in communication with the first plurality of bond pads, the second plurality of bond pads, and the apertures of the discrete preformed blank.

24. The method of claim 23, further including forming the circuit traces to extend at least partially between the wafer-size discrete preformed blank and the at least some semiconductor dice.

25. The method of claim 23, further including forming the circuit traces to extend at least partially on a surface of the wafer-size discrete preformed blank which remains exposed after the discrete preformed blank and the wafer-size discrete preformed wafer is assembled.

26. The method of claim 23, further comprising forming the wafer of a semiconductor material and forming the provided wafer-size discrete preformed blank of the same semiconductor material as the wafer.

27. The method of claim 23, further comprising:

fabricating an integrated circuit including external electrical connections on the active surfaces of the at least some semiconductor dice.

28. The method of claim 23, further comprising:

providing a die-attach material; and

wherein assembling the wafer-size discrete preformed blank to the wafer comprises bonding the wafer-size discrete preformed blank with the die-attach material to the plurality of semiconductor dice of the wafer.

29. The method of claim 28, wherein the bonding of the wafer-size discrete preformed blank with the die-attach material to the plurality of semiconductor dice of the wafer comprises the plurality of semiconductor dice remaining unsevered from the wafer and the wafer-size discrete preformed blank remaining unsevered.

30. The method of claim 28, further comprising, after burning-in and testing, severing the at least some of the plurality of semiconductor dies with corresponding portions of the wafer-size discrete preformed blank so as to have selected surface dimensions not in excess of surface dimensions of the active surface of the severed semiconductor dies.

31. The method of claim 30, further including singulating the semiconductor dies with attached die-size discrete preformed blanks from the bonded wafer and wafer-size discrete preformed blank.

32. A method of claim 30, wherein forming the second plurality of bond pads comprises forming at least one of the second plurality of bond pads on a face of the wafer-size discrete preformed blank.

33. The method of claim 30, wherein forming the second plurality of bond pads comprises forming the second plurality of bond pads on a back side of the wafer-size discrete preformed blank.

34. The method of claim 33, wherein forming apertures in the wafer-size discrete preformed blank comprises micromaching the apertures in a front face of the wafer-size discrete preformed blank.

35. The method of claim 33, wherein forming the second plurality of bond pads and forming the circuit traces on the back side of the wafer-size discrete preformed blank comprises applying a conductor-carrying dielectric film to at least a portion of the back side of the wafer-sized discrete preformed blank.

36. The method of claim 30, wherein forming the second plurality of bond pads at a second plurality of positions comprises locating the second plurality of positions generally along a selected common edge of each of the at least some semiconductor dice and corresponding portions of the wafer-size discrete preformed blank.

37. The method of claim 36, further comprising forming a plurality of mutually parallel trenches extending generally perpendicularly from the selected common edge of each of the at least some semiconductor dice and corresponding portions of the wafer-size discrete preformed blank and being communicative with the apertures of the wafer-size discrete preformed blank.

38. The method of claim 30, further comprising forming the wafer of a semiconductor material comprising silicon and forming the provided wafer-size discrete preformed blank of the same semiconductor material comprising silicon as the wafer.

39. The method of claim 28, further comprising forming the wafer of a semiconductor material comprising silicon and forming the provided wafer-size discrete preformed blank of the same semiconductor material comprising silicon as the wafer.

40. The method of claim 23, further including bonding the wafer-size discrete preformed blank to the plurality of semiconductor dice to form a substantially hermetic seal.

41. The method of claim 23, further comprising disposing a conductive material in at least one of the of apertures of the wafer-size discrete preformed blank.

42. The method of claim 23, further comprising, after burning-in and testing, severing the at least some of the plurality of semiconductor dies with corresponding portions of the wafer-size discrete preformed blank so as to have selected surface dimensions not in excess of surface dimensions of the active surface of the severed semiconductor dies.

43. The method of claim 42, further including singulating the semiconductor dies with attached die-size discrete blanks from the assembled wafer and wafer-size discrete preformed blank.