Electron beam process during dual damascene processing

• US 6,207,555 B1
• Filed: 03/17/1999
• Issued: 03/27/2001
• Est. Priority Date: 03/17/1999
• Status: Expired due to Term

• Current Assignee: Electron Vision Corp (Honeywell International Inc.)
• Original Assignee: Electron Vision Corp (Honeywell International Inc.)
• Inventors: Ross, Matthew F.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): BERRY, RENEE R
• Application Number:
  US09/270,536
• Time in Patent Office: 741 Days
• Field of Search: 438/633, 438/618, 438/669, 438/672, 438/702, 438/751, 438/752, 438/762
• US Class Current: 438/633
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.

Claims

1. A process for producing a microelectronic device which comprises:

(a) applying a dielectric layer onto a substrate;

(b) overall exposing the dielectric layer to electron beam irradiation under conditions sufficient to cure an upper portion of the dielectric layer and render the upper portion a polish stop layer while not substantially curing a lower portion of the dielectric layer;

(c) imagewise patterning the dielectric layer to form vias in the dielectric layer extending to the substrate;

(d) depositing a metal into the vias and onto a top surface of the dielectric layer;

(e) removing the metal from the top surface of the dielectric layer.

2. The process of claim 1 wherein the removing of metal from the top surface of the dielectric layer is conducted by chemical mechanical polishing or etching back the metal on the top surface until the polish stop layer is reached.

3. The process of claim 1 wherein the dielectric layer comprises a silicon containing polymer an alkoxysilane polymer, a silsesquioxane polymer, a siloxane polymer, a poly(arylene ether), a fluorinated poly(arylene ether), a nanoporous silica or combinations thereof.

4. The process of claim 1 wherein the substrate comprises gallium arsenide (GaAs), germanium, silicon, silicon germanium, lithium niobate and compositions containing silicon and combinations thereof.

5. The process of claim 1 wherein the electron beam exposing step is conducted at an energy level ranging from about 1 to about 30 KeV.

6. The process of claim 1 wherein the electron beam exposing step is conducted at an electron dose ranging from about 50 to about 50,000 μ

C/cm².

7. The process of claim 1 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a large-area electron beam source.

8. The process of claim 1 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a uniform large-area electron beam source which covers an area of from about 4 square inches to about 256 square inches.

9. The process of claim 1, wherein the metal is selected from the group consisting of aluminum, aluminum alloys, copper, copper alloys, tantalum, tungsten and titanium.

10. A process for producing a microelectronic device which comprises:

(a) applying a first dielectric layer onto a substrate;

(b) applying a second dielectric layer onto the first dielectric layer;

(c) overall exposing the second dielectric layer to electron beam irradiation under conditions sufficient to cure the second dielectric layer and render the second dielectric layer a polish stop layer while not substantially curing the first dielectric layer;

(d) imagewise patterning the first and second dielectric layers to form vias in the first and second dielectric layers extending to the substrate;

(e) depositing a metal into the vias and onto a top surface of the second dielectric layer;

(f) removing the metal from the top surface of the second dielectric layer.

11. The process of claim 10 wherein the removing of metal from the top surface of the second dielectric layer is conducted by chemical mechanical polishing or etching back the metal on the top surface until the polish stop layer is reached.

12. The process of claim 10 wherein each dielectric layer comprises a silicon containing polymer an alkoxysilane polymer, a silsesquioxane polymer, a siloxane polymer, a poly(arylene ether), a fluorinated poly(arylene ether), a nanoporous silica or combinations thereof.

13. The process of claim 10 wherein the substrate comprises gallium arsenide (GaAs), germanium, silicon, silicon germanium, lithium niobate and compositions containing silicon and combinations thereof.

14. The process of claim 10 wherein the electron beam exposing step is conducted at an energy level ranging from about 1 to about 30 KeV.

15. The process of claim 10 wherein the electron beam exposing step is conducted at an electron dose ranging from about 50 to about 50,000 μ

C/cm².

16. The process of claim 10 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a large-area electron beam source.

17. The process of claim 10 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a uniform large-area electron beam source which covers an area of from about 4 square inches to about 256 square inches.

18. The process of claim 10, wherein the metal is selected from the group consisting of aluminum, aluminum alloys, copper, copper alloys, tantalum, tungsten and titanium.

19. A process for producing a microelectronic device which comprises:

(a) applying a first dielectric layer onto a substrate;

(b) overall exposing the first dielectric layer to electron beam irradiation under conditions sufficient to cure an upper portion of the first dielectric layer and render the upper portion of the first dielectric layer an etch stop layer while not substantially curing a lower portion of the first dielectric layer;

(c) applying a second dielectric layer onto the first dielectric layer;

(d) overall exposing an upper portion of the second dielectric layer to electron beam irradiation under conditions sufficient to cure the upper portion of the second dielectric layer and render the upper portion of the second dielectric layer a polish stop layer while not substantially curing a lower portion of the second dielectric layer;

(e) imagewise patterning the second dielectric layer to form trenches in the dielectric layers extending to the first dielectric layer;

(f) imagewise patterning the first dielectric layer to form vias in the first dielectric layer extending to the substrate;

(g) depositing a metal into the vias, trenches and onto a top surface of the second dielectric layer;

(h) removing the metal from the top surface of the second dielectric layer.

20. The process of claim 19 wherein the removing of metal from the top surface of the second dielectric layer is conducted by chemical mechanical polishing or etching back the metal on the top surface until the polish stop layer is reached.

21. The process of claim 19 wherein each dielectric layer comprises a silicon containing polymer an alkoxysilane polymer, a silsesquioxane polymer, a siloxane polymer, a poly(arylene ether), a fluorinated poly(arylene ether), a nanoporous silica or combinations thereof.

22. The process of claim 19 wherein the substrate comprises gallium arsenide (GaAs), germanium, silicon, silicon germanium, lithium niobate and compositions containing silicon and combinations thereof.

23. The process of claim 19 wherein the electron beam exposing step is conducted at an energy level ranging from about 1 to about 30 KeV.

24. The process of claim 19 wherein the electron beam exposing step is conducted at an electron dose ranging from about 50 to about 50,000 μ

C/cm².

25. The process of claim 19 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a large-area electron beam source.

26. The process of claim 19 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a uniform large-area electron beam source which covers an area of from about 4 square inches to about 256 square inches.

27. The process of claim 19, wherein the metal is selected from the group consisting of aluminum, aluminum alloys, copper, copper alloys, tantalum, tungsten and titanium.

28. A process for producing a microelectronic device which comprises:

(a) applying a first dielectric layer onto a substrate;

(b) applying a second dielectric layer onto the first dielectric layer;

(c) overall exposing the second dielectric layer to electron beam irradiation under conditions sufficient to cure the second dielectric layer and render the second dielectric layer an etch stop layer while not substantially curing the first dielectric layer;

(d) applying a third dielectric layer onto the second dielectric layer;

(e) applying a fourth dielectric layer onto the third dielectric layer;

(f) overall exposing the fourth dielectric layer to electron beam irradiation under conditions sufficient to cure the fourth dielectric layer and render the fourth dielectric layer a polish stop layer while not substantially curing the third dielectric layer;

(g) imagewise patterning the third and fourth dielectric layers to form trenches in the third and fourth dielectric layers extending to the second dielectric layer;

(h) imagewise patterning the first and second dielectric layers to form vias in the first and second dielectric layers extending to the substrate;

(i) depositing a metal into the vias, trenches and onto a top surface of the fourth dielectric layer;

(j) removing the metal from the top surface of the fourth dielectric layer.

29. The process of claim 28 wherein the removing of metal from the top surface of the fourth dielectric layer is conducted by chemical mechanical polishing or etching back the metal on the top surface until the polish stop layer is reached.

30. The process of claim 28 wherein the dielectric layer comprises a silicon containing polymer an alkoxysilane polymer, a silsesquioxane polymer, a siloxane polymer, a poly(arylene ether), a fluorinated poly(arylene ether), a nanoporous silica or combinations thereof.

31. The process of claim 28 wherein the substrate comprises gallium arsenide (GaAs), germanium, silicon, silicon germanium, lithium niobate and compositions containing silicon and combinations thereof.

32. The process of claim 28 wherein the electron beam exposing step is conducted at an energy level ranging from about 1 to about 30 KeV.

33. The process of claim 28 wherein the electron beam exposing step is conducted at an electron dose ranging from about 50 to about 50,000 μ

C/cm².

34. The process of claim 28 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a large-area electron beam source.

35. The process of claim 28 wherein the electron beam exposing step is conducted with a wide, large beam of electron beam radiation from a uniform large-area electron beam source which covers an area of from about 4 square inches to about 256 square inches.

36. The process of claim 28, wherein the metal is selected from the group consisting of aluminum, aluminum alloys, copper, copper alloys, tantalum, tungsten and titanium.

37. A process for producing a microelectronic device which comprises:

(a) applying a first dielectric layer onto a substrate;

(b) overall exposing the first dielectric layer to electron beam irradiation under conditions sufficient to cure an upper portion of the first dielectric layer and render the upper portion of the first dielectric layer an etch stop layer while not substantially curing a lower portion of the first dielectric layer;

(c) imagewise patterning the irradiated portion of the first dielectric layer to form vias extending to the lower portion of the first dielectric layer;

(d) applying a second dielectric layer onto the first dielectric layer;

(e) exposing an upper portion of the second dielectric layer to electron beam irradiation under conditions sufficient to cure the upper portion of the second dielectric layer and render the upper portion of the second dielectric layer a polish stop layer while not substantially curing a lower portion of the second dielectric layer;

(f) imagewise patterning the second dielectric layer to form trenches in the second dielectric layers and vias in the first dielectric layer extending to the substrate;

(g) depositing a metal into the vias, trenches and onto a top surface of the second dielectric layer;

(h) removing the metal from the top surface of the second dielectric layer.

38. A process for producing a microelectronic device which comprises:

(a) applying a first dielectric layer onto a substrate;

(b) applying a second dielectric layer onto the first dielectric layer;

(c) overall exposing the second dielectric layer to electron beam irradiation under conditions sufficient to cure the second dielectric layer and render the second dielectric layer an etch stop layer while not substantially curing the first dielectric layer;

(d) imagewise patterning the second dielectric layer to form vias extending to the first dielectric layer;

(e) applying a third dielectric layer onto the second dielectric layer;

(f) applying a fourth dielectric layer onto the third dielectric layer;

(g) overall exposing the fourth dielectric layer to electron beam irradiation under conditions sufficient to cure the fourth dielectric layer and render the fourth dielectric layer a polish stop layer while not substantially curing the third dielectric layer;

(h) imagewise patterning the third and fourth dielectric layers to form trenches in the third and fourth dielectric layers and vias in the first and second dielectric layer extending to the substrate;

(i) depositing a metal into the vias, trenches and onto a top surface of the fourth dielectric layer;

(j) removing the metal from the top surface of the fourth dielectric layer.