Differential signal transmission circuit

• US 6,208,161 B1
• Filed: 12/28/1998
• Issued: 03/27/2001
• Est. Priority Date: 01/09/1998
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Suda, Masakatsu
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/221,498
• Time in Patent Office: 820 Days
• Field of Search: 326/30, 326/86, 326/90, 326/82, 333/22.R
• US Class Current: 326/30
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A differential signal transmission circuit for transmitting a high speed pulse signal through relatively long transmission cables. The differential signal transmission circuit includes a CMOS differential driver for receiving a high speed signal to be transmitted from an LSI circuit and providing the signal to a differential transmission cable, an impedance matching circuit connected between an output of the CMOS differential driver and ground to substantially decrease an output impedance of the driver, and a series termination circuit provided between the output of the CMOS differential driver and the differential transmission cable to match a sum of resistance of the series transmission circuit and an overall impedance at the output of the driver with a characteristic impedance of the differential transmission cable.

Claims

1. A differential signal transmission circuit for transmitting a high speed signal through a differential transmission line, comprising:

a CMOS (Complementary Metal Oxide Semiconductor) differential driver for receiving a high speed signal to be transmitted from an LSI circuit and providing the signal to a differential transmission cable;

an impedance matching circuit connected between an output of the CMOS differential driver and ground to substantially decrease an output impedance of the CMOS differential driver; and

a series termination circuit provided between the output of the CMOS differential driver and the differential transmission cable to match a sum of resistance of the series transmission circuit and an overall impedance at the output of the CMOS differential driver with a characteristic impedance of the differential transmission cable.

2. A differential signal transmission circuit as defined in claim 1, wherein the CMOS differential driver is integrated into the LSI circuit at an output stage of the LSI circuit which is a CMOS integrated circuit.

3. A differential signal transmission circuit as defined in claim 1, further comprising a differential receiver provided at an end of the differential transmission cable opposite to the CMOS differential driver for receiving and reproducing the high speed signal through the differential transmission cable, and a receiver resistor connected at an input of the differential receiver to match an input impedance of the differential receiver with the characteristic impedance of the differential transmission cable.

4. differential signal transmission circuit as defined in claim 1, wherein the series termination circuit includes a termination resistor provided in series with the differential transmission cable, and a peaking circuit for compensating a high frequency signal transmission characteristics of the differential signal transmission circuit.

5. A differential signal transmission circuit as defined in claim 4, wherein the series resistor and the peaking circuit are connected in parallel with each other, and the peaking circuit is formed of a resistor and a capacitor series connected with each other.

6. A differential signal transmission circuit as defined in claim 4, wherein the high speed signal is a pulse signal whose delays in transition times of leading and trailing edges are compensated by the peaking circuit.

7. A differential signal transmission circuit for transmitting a high speed signal through a differential transmission line, comprising:

a plurality of transmission channels for transmitting high speed pulse signals generated by an LSI circuit, each of the transmission channel is comprised of;

a CMOS (Complementary Metal Oxide Semiconductor) differential driver for receiving a high speed signal to be transmitted from the LSI circuit and providing the high speed signal to a differential transmission cable;

an impedance matching circuit connected between an output of the CMOS differential driver and ground to substantially decrease an output impedance of the CMOS differential driver;

a series termination circuit provided between the output of the CMOS differential driver and the differential transmission cable to match a sum of resistance of the series transmission circuit and an overall impedance at the output of the driver with a characteristic impedance of the differential transmission cable; and

a differential receiver provided at an end of the differential transmission cable for receiving and reproducing the high speed signal through the differential transmission cable;

wherein the CMOS differential driver in each transmission channel is integrated into the LSI circuit, and wherein the LSI circuit is a CMOS integrated circuit.

8. A differential signal transmission circuit as defined in claim 7, wherein each of the transmission channel is further comprised of a receiver resistor connected at an input of the differential receiver to match an input impedance of the differential receiver with the characteristic impedance of the differential transmission cable.

9. A differential signal transmission circuit as defined in claim 7, wherein the series termination circuit in each of the transmission channel includes a termination resistor provided in series with the differential transmission cable, and a peaking circuit for compensating a high frequency signal transmission characteristics of the differential signal transmission circuit.

10. A differential signal transmission circuit as defined in claim 9, wherein the series resistor and the peaking circuit are connected in parallel with each other, and the peaking circuit is formed of a resistor and a capacitor series connected with each other.

11. A differential signal transmission circuit as defined in claim 9, wherein delays in transition times of leading and trailing edges of the high speed pulse signal are compensated by the peaking circuit.