Programmable logic array with vertical transistors
First Claim
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1. A programmable logic array, comprising:
- a first logic plane that receives a number of input signals, the first logic plane having a plurality of vertical transistors, each having a first source/drain region, a body region and a second source/drain region, wherein the vertical transistors include one gate that is formed in a trench adjacent to the body region and have a body contact that is formed adjacent to the body region on a side opposite the gate, wherein the body contact is pulsed in synchronization with the gate, and wherein the vertical transistors are arranged in rows and columns that are interconnected to provide a number of logical outputs; and
a second logic plane having a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
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Abstract
A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
246 Citations
30 Claims
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1. A programmable logic array, comprising:
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a first logic plane that receives a number of input signals, the first logic plane having a plurality of vertical transistors, each having a first source/drain region, a body region and a second source/drain region, wherein the vertical transistors include one gate that is formed in a trench adjacent to the body region and have a body contact that is formed adjacent to the body region on a side opposite the gate, wherein the body contact is pulsed in synchronization with the gate, and wherein the vertical transistors are arranged in rows and columns that are interconnected to provide a number of logical outputs; and
a second logic plane having a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer system, comprising:
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at least one input/output device;
a memory; and
a central processing unit, the central processing unit coupled to the memory and the at least one input/output device, the central processing unit including at least one programmable logic array including;
a first logic plane that receives a number of input signals, the first logic plane having a plurality of vertical transistors, each having a first source/drain region, a body region and a second source/drain region, wherein the vertical transistors include one gate that is formed in a trench adjacent to the body region and have a body contact that is formed adjacent to the body region on a side opposite the gate, wherein the body contact is pulsed in synchronization with the gate, and wherein the vertical transistors are arranged in rows and columns that are interconnected to provide a number of logical outputs; and
a second logic plane having a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function for the central processing unit. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification