Low jitter phase locked loop having a sigma delta modulator and a method thereof

• US 6,208,211 B1
• Filed: 09/24/1999
• Issued: 03/27/2001
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moshe, David, Zarubinsky, Michael, Zipper, Eliav, Afek, Yachin
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/406,014
• Time in Patent Office: 550 Days
• Field of Search: 331/17, 331/25, 331/57
• US Class Current: 331/17
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.

Claims

1. A phase lock loop comprising:

a current controlled oscillator, adapted to provide an output signal ICOS having a frequency of Fico, wherein Fico is controlled by a current input signal Idac, the current controlled oscillator having an input resistance Rin;

Rin is proportional to Idac;

a frequency divider, coupled to the current controlled oscillator, for receiving ICOS and providing a frequency divider output signal FD, the frequency of FD is Ffd and Ffd=(Fico/N), N>

0;

a phase detector, coupled to the frequency divider and adapted to be coupled to a reference signal for receiving a reference signal REF, REF having a frequency of Fref;

wherein the phase detector receives REF and FD and provides an error signal ERS that reflects the phase difference between REF and FD;

a loop filter, coupled to the phase detector;

for filtering ERS;

a sigma delta modulator, coupled to the loop filter, for performing sigma delta modulations upon the output signal of the loop filter, and for providing a digital sigma delta modulated control signal SDO;

a digital to analog converter, coupled to the sigma delta modulator and to the current controlled oscillator, for converting SDO to Idac and providing Idac to the current controlled oscillator; and

a capacitor, coupled to the current controlled oscillator, the capacitor and Rin generate a pole Fpole in the transfer function of the phase locked loop.

2. The phase locked loop of claim 1 wherein the sigma delta modulator sampling rate is Fico, the sigma delta modulator forces error signal outside a predetermined frequency BWsd;

and

wherein Fpole tracks BWsd.

3. The phase lock loop of claim 2 wherein the sigma delta modulator is of second order.

4. The phase lock loop of claim 3 wherein the current controlled oscillator is comprised of a odd number of inverters;

the inverters are cascaded and the output of a last inverter ic coupled to the input of a first inverter;

wherein each inverter is comprised of an n-channel CMOS transistor and a p-channel CMOS transistor.

5. A method for providing a low jitter phase locked signal from a phase locked loop, the method comprising of the steps of:

receiving an external reference signal REF and a divided output signal FD, wherein a current controlled oscillator provides a frequency output signal ICOS having a frequency of Fico, the frequency output signal ICOS is provided to a frequency divider, the frequency divider provides the divided output signal FD, FD having a frequency of Ffd, Ffd being a fraction (1/N) of Fico;

providing an error signal ERS reflecting the phase difference between REF and FD;

filtering the error signal ERS;

performing a sigma delta modulation upon ERS, providing a digital sigma delta control signal SDO and forcing error signals outside a predetermined frequency BWsd;

converting the digital sigma delta control signal SDO to an analog signal Idac and providing Idac to the current controlled oscillator and a capacitor, the current controlled oscillator and the capacitor introduce a pole Fpole in a transfer function of the phase locked loop, wherein Fpole tracks BWsd; and

smoothing Idac and converting the smoothed Idac signal to the frequency output signal, wherein Fico is dependent upon the smoothed Idac.

6. The method of claim 5 wherein ERS if filtered by passing ERS through a digital integrator.