Content addressable memory cell providing simultaneous read and compare capability

• US 6,208,544 B1
• Filed: 09/09/1999
• Issued: 03/27/2001
• Est. Priority Date: 09/09/1999
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Beadle, Edward R., Dishman, John F.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/391,918
• Time in Patent Office: 565 Days
• Field of Search: 365/49, 365/189.07
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

The need to employ three separate cycles for write, read and compare operations for operation of a content addressable memory cell is obviated by a memory cell architecture that allows simultaneous read and compare operations, thereby reducing memory cycle time by one-third of that of a conventional CAM. To enable the data bit stored in the memory cell to be compared with a reference bit, the memory cell is coupled with a comparator, that receives inputs from the data nodes of the memory cell and a set of comparison bit input lines. Rather than supplying reference data by way of the data lines through which data is written into and read from the memory cell, as in a conventional CAM, the compare bit and its complement are coupled to the match logic exclusively of the memory cell. Since application of the comparison bit does not involve the use of the normal data read and write lines, accessing data read and write paths for the memory cell is not required. As a consequence, a read cycle and a comparison cycle may be performed simultaneously, without one affecting the other.

Claims

1. A content addressable memory comprising:

a data bit storage cell;

a data input through which a data bit is written into said data bit storage cell during a write cycle;

a data output through which the data bit stored in said data bit storage cell is read out therefrom during a read cycle;

an address circuit through which said data bit storage cell is selectively accessed during said read and write cycles; and

a data bit comparator coupled to said data bit storage cell and being configured to determine whether the data bit stored in said data bit storage cell matches a data reference bit that is applied thereto, simultaneously with the reading out of the data bit in accordance with selective accessing of said bit storage cell by said address circuit during said read cycle, and also to determine whether the data bit stored in said data bit storage cell matches a data reference bit that is applied thereto irrespective of whether or not said data bit storage cell is accessed by said address circuit to read out the data bit stored therein.

2. A content addressable data bit storage cell according to claim 1, wherein

said data bit storage cell comprises first and second cross-coupled inverters having respective first and second data nodes, and

said address circuit comprises first and second address switches respectively coupled in circuit with said first and second data nodes and first and second data access nodes; and

further including

a data input switch coupled in circuit with said data input and said first data access node; and

a data output switch coupled in circuit with said data output and said data access node; and

wherein

said data bit comparator has first and second compare input nodes coupled to said first and second data nodes, and first and second reference nodes that are respectively coupled to receive said data reference bit and the complement of said data reference bit, and an output node having a logic state representative of whether or not said data bit stored by said data bit storage cell matches said data reference bit.

3. A memory cell comprising:

a data bit storage cell having a data input through which a data bit is written into said data bit storage cell, a data output through which a data bit is read out of said data bit storage cell, and an address input through which said data bit storage cell is selectively accessed; and

a data bit comparator coupled to said data bit storage cell and being configured to determine whether the data bit stored in said data bit storage cell matches a reference data bit that is applied thereto during selective accessing of sid bit storage cell by said address circuit for a read cycle for said data bit storage cell, and also to determine whether the data bit stored in said data bit storage cell matches a data reference bit that is applied thereto irrespective of whether or not said data bit storage cell is accessed by said address circuit to read out the data bit stored therein.

4. A method of operating a data bit storage cell having a data input through which a data bit is written into said data bit storage cell, a data output through which a data bit is read out of said data bit storage cell, and an address input through which said data bit storage cell is selectively accessed during read and write cycles, said method comprising:

(a) during a read cycle, selectively accessing said data bit storage cell by way of said address input thereof, and thereby reading out said data bit from said data bit storage cell and also determining whether the data bit stored in said data bit storage cell matches a reference data bit; and

(b) irrespective of selective accessing of said data bit storage cell by way of said address input thereof, determining whether the data bit stored in said data bit storage cell matches a reference data bit.

5. A memory cell comprising:

a data bit storage cell containing first and second cross-coupled inverters having respective first and second data nodes, and first and second address switches coupled in circuit with said first and second data nodes and first and second data access nodes;

a data input switch coupled in circuit with a data input node and said first data access node;

a data output switch coupled in circuit with a data output node and said data access node; and

a comparator having first and second compare input nodes coupled to said first and second data nodes, and first and second reference nodes respectively coupled to receive a data reference bit to be compared and the complement of said data reference bit to be compared, exclusive of operation of either of said first and second address switches and thereby signal paths to said first and second data access nodes, and an output node having a logic state representative of whether or not said data bit stored by said data bit storage cell matches said data reference bit irrespective of said operation of either of said first and second address switches.

6. A memory cell according to claim 5, wherein said comparator is configured to determine whether the data bit stored in said data bit storage cell matches said data reference bit during a read cycle for said data bit storage cell.