One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS

• US 6,208,549 B1
• Filed: 02/24/2000
• Issued: 03/27/2001
• Est. Priority Date: 02/24/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Voogel, Martin L., Rao, Kameswara K.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/513,235
• Time in Patent Office: 397 Days
• Field of Search: 365/96, 365/103, 365/104, 365/148, 365/225.7, 365/207, 365/208, 327/525
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A memory system is provided for accessing an array of polycide fuses. The memory system includes an access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuitry is provided to selectively connect one of the polycide fuses to the access control circuit in response to an address signal. In one embodiment, the access control circuit includes a partial sense amplifier circuit, which is completed by connecting one of the polycide fuses to the partial sense amplifier circuit. The completed sense amplifier circuit compares the resistance of the connected polycide fuse with a reference resistance to determine the state of the polycide fuse. The completed sense amplifier circuit provides an output signal representative of the state of the connected polycide fuse. The access control circuit also includes a programming transistor connected between an input/output supply voltage (V_IO) and the partial sense amplifier circuit. The V_IO supply voltage is greater than the V_DD supply voltage. When the programming transistor is turned on, the V_IO supply voltage is applied to the connected polycide fuse. Under these conditions, the resistance of the connected polycide fuse significantly increases, thereby programming the polycide fuse.

Claims

1. A non-volatile memory system comprising:

a plurality of memory circuits, wherein each of the memory circuits includes;

a sense amplifier circuit that includes a polycide fuse element;

a first access transistor for enabling the sense amplifier circuit, the first access transistor being connected in series with the polycide fuse element; and

a second access transistor for applying a programming voltage to the polycide fuse element, the second access transistor being connected in series with the polycide fuse element; and

a decoder circuit coupled to the first access transistor in each of the memory circuits, wherein the decoder circuit is configured to selectively enable one of the first access transistors in response to an address signal.

2. The memory system of claim 1, wherein the memory system is fabricated on a chip having core logic that is powered by a V_DD supply voltage and input/output logic that is powered by a V_IO supply voltage, the V_IO supply voltage being greater than the V_DD supply voltage, wherein the V_IO supply voltage is used as the programming voltage.

3. The memory system of claim 1, wherein the second access transistor in each of the memory circuits is commonly connected to receive a programming control signal.

4. The memory system of claim 1, wherein each sense amplifier circuit further comprises a first set of series-connected transistors and a second set of series-connected transistors.

5. The memory system of claim 4, wherein each sense amplifier circuit further comprises the polycide fuse element and the first access transistor connected in series with the first set of series-connected transistors, and a resistor connected in series with the second set of series-connected transistors, wherein the resistor has a greater resistance than the polycide fuse element before the polycide fuse element is programmed, and wherein the resistor has a lower resistance than the polycide fuse element after the polycide fuse element is programmed.

6. The memory system of claim 1, wherein each first access transistor is a high-voltage transistor.

7. The memory system of claim 1, wherein each second access transistor is a high-voltage transistor.

8. A memory system comprising:

an array of polycide fuse elements arranged in at least one row and a plurality of columns;

an access control circuit for individually reading and programming each of the polycide fuse elements;

a plurality of bit lines, wherein each of the columns of polycide fuse elements is connected to a corresponding one of the bit lines;

a column decoder circuit configured to selectively couple one of the bit lines to the access control circuit in response to an address signal; and

a row decoder circuit configured to selectively couple the polycide fuse elements in a row of the array between the corresponding one of the bit lines and a voltage supply terminal in response to an address signal.

9. The memory system of claim 8, wherein the access control circuit comprises:

a partial sense amplifier circuit, wherein the partial sense amplifier circuit is completed by connection to one of the polycide fuse elements; and

a programming transistor coupled to receive a programming voltage.

10. The memory system of claim 9, wherein the column decoder circuit is configured to selectively couple one of the bit lines to the partial sense amplifier circuit and the programming transistor in response to an address signal.

11. The memory system of claim 9, wherein the partial sense amplifier circuit comprises a first set of series connected transistors and a second set of series-connected transistors.

12. The memory system of claim 11, wherein the partial sense amplifier circuit further comprises a resistor connected in series with the second set of series-connected transistors, wherein the resistor has a greater resistance than each of the polycide fuse elements before the polycide fuse elements are programmed, and wherein the resistor has a lower resistance than the polycide fuse elements after the polycide fuse elements are programmed.

13. The memory system of claim 12, wherein the first set of series-connected transistors is connected to the column decoder circuit.

14. The memory system of claim 8, wherein the column decoder circuit comprises a plurality of access transistors, wherein each of the access transistors is connected between the access control circuit and a corresponding one of the bit lines.

15. The memory system of claim 8, wherein the row decoder circuit comprises a plurality of access transistors, wherein each of the access transistors is connected in series with a corresponding one of the polycide fuse elements.

16. A one-time programmable memory circuit fabricated on a chip, the memory circuit comprising:

a V_DD supply terminal configured to supply a V_DD supply voltage to core logic on the chip;

a V_IO supply terminal configured to provide a V_IO supply voltage to input/output logic on the chip, wherein the V_IO supply voltage is greater than the V_DD supply voltage;

a polycide fuse; and

an access control circuit for programming and reading the polycide fuse, the access control circuit being configured to couple the V_IO supply terminal to the polycide fuse during programming, the access control circuit further being configured to couple the V_DD supply terminal to the polycide fuse during reading.

17. The one-time programmable memory circuit of claim 16, wherein the access control circuit comprises a high voltage transistor coupled between the V_IO supply terminal and the polycide fuse.

18. The one-time programmable memory circuit of claim 16, wherein the access control circuit comprises a sense amplifier circuit.

19. A method of accessing an array of polycide fuses arranged in at least one row and a plurality of columns, the method comprising the steps of:

selectively coupling one of the columns of polycide fuses to a partial sense amplifier circuit and a programming transistor in response to an address signal; and

selectively coupling each of the polycide fuses in a row to a voltage supply terminal in response to an address signal.