Semiconductor memory device having resistive bitline contact testing

• US 6,208,572 B1
• Filed: 06/12/2000
• Issued: 03/27/2001
• Est. Priority Date: 06/12/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rudgers, George E., Pilo, Harold, Adams, R. Dean, Busch, Robert E.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/592,055
• Time in Patent Office: 288 Days
• Field of Search: 365/201, 365/63, 365/190, 365/154
• US Class Current: 365/201
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.

Claims

1. A memory device comprising:

a first and second memory cell;

a bitline for transferring a data value to or from said first and second memory cell;

a bitline contact coupling said bitline to said first and second memory cell;

a first and second wordline signal for activating said first and second memory cell, respectively, to transfer said data value to said bitline; and

a wordline logic device, receiving said first and second wordline signal and transmitting said first and second wordline signal to said first and second memory cell, respectively,

wherein during a test of said bitline contact, said wordline logic device transmits said first and second wordline signal to said first and second memory cell essentially simultaneously.

2. The memory device of claim 1, wherein said first memory cell further comprises:

a first pass gate, coupled to said bitline contact and said wordline logic device, for passing on said data value to said bitline when activated by said first wordline signal; and

a first cell latch coupled to said first pass gate for holding said data value until said first pass gate is activated.

3. The memory device of claim 1, wherein said second memory cell further comprises:

a second pass gate, coupled to said bitline contact and said wordline logic device, for passing on said data value to said bitline when activated by said second wordline signal; and

a second cell latch coupled to said second pass gate for holding said data value until said second pass gate is activated.

4. The memory device of claim 1, further comprising a test cell connected at a substantially central location of said bitline.

5. The memory device of claim 4, wherein said test cell further comprises:

a test pass gate coupled to said bitline, for passing on a second data value to said bitline when activated by a test wordline signal; and

a test cell latch coupled to said test pass gate for holding said second data value until said test pass gate is activated,

wherein said test cell is activated essentially simultaneously to the activation of said first and second memory cell.

6. The memory device of claim 5, wherein for a test mode a same data value is written into said first and second memory cell.

7. The memory device of claim 6, wherein said second data value is a complement of said data value written into said first and second memory cell.

8. The memory device of claim 1, wherein said first memory cell is adjacent to said second memory cell, and said first and second memory cell share said bitline contact.

9. A method for testing the resistance of a bitline contact in a memory device having memory cells comprising the steps of:

a) writing a data value into adjacent memory cells sharing said bitline contact;

b) reading said data value from said adjacent memory cells essentially simultaneously; and

c) comparing said read data value of said adjacent memory cells with said written data value.

10. The method of claim 9, wherein step b) further comprises the steps of:

b1) providing a wordline logic device;

b2) transmitting a first and second wordline signal to said adjacent memory cells simultaneously with said wordline logic device; and

b3) activating said adjacent memory cells essentially simultaneously with said first and second wordline signal.

11. The method of claim 9, further comprising the steps of:

d) providing a test cell;

e) writing a same data value into said adjacent memory cells;

f) writing a complementary value of said data value into said test cell; and

g) reading said test cell essentially simultaneously to the reading of said adjacent memory cells.

12. The method of claim 11, further comprising the steps of:

h) comparing said data value read from said adjacent memory cells to said value read from said test cell; and

i) detecting a resistive bitline contact when said data value read from said adjacent memory cells is different than said value read from said test cell.

13. A SRAM memory array system comprising:

a plurality of adjacent memory cells;

a bitline pair for transferring data values to or from said plurality of adjacent memory cells;

a plurality of bitline contacts coupling said bitline pair to said plurality of adjacent memory cells, each of said plurality of bitline contacts being shared between each of said plurality of adjacent memory cells, respectively;

a plurality of wordline signals for activating said plurality of adjacent memory cells, for transferring said data values to said bitline pair; and

a plurality of wordline logic devices, receiving said plurality of wordline signals, each of said plurality of wordline logic devices receiving two of said plurality of wordline signals, and transmitting said plurality of wordline signals to said plurality of adjacent memory cells,

wherein during a test of each of said plurality of bitline contacts, each of said plurality of wordline logic devices transmits said two of said plurality of wordline signals to each of said plurality of adjacent memory cells essentially simultaneously.

14. The system of claim 13, wherein each of said plurality of adjacent memory cells further comprises:

a first and second pass gate, coupled to one of said plurality of bitline contacts and to one of said plurality of wordline logic devices, for passing on data values to said bitline pair when activated by said one of said plurality of wordline signals;

a first cell latch coupled to said first pass gate, for holding a first data value until said first pass gate is activated; and

a second cell latch coupled to said second pass gate for holding a second data value until said second pass gate is activated.

15. The system of claim 13, further comprising a test cell connected at a substantially central location of said bitline pair.

16. The system of claim 15, wherein said test cell further comprises:

a test pass gate coupled to said bitline pair, for passing on a third data value to one of said bitline pair when activated by a test wordline signal; and

a test cell latch coupled to said test pass gate for holding said second data value until said test pass gate is activated,

wherein said test cell is activated essentially simultaneously to the activation of each of said plurality of adjacent memory cells.

17. The system of claim 16, wherein for test mode said first and second data value are the same value.

18. The system of claim 17, wherein said third data value is a complement of said first and second data value.

19. The system of claim 13, wherein said bitline pair comprises:

a true bitline for transferring a true value of said data values; and

a complementary bitline for transferring a complementary value of said data values.

20. The system of claim 13, wherein a resistance of each of said plurality of adjacent memory cells during test mode is half the resistance of said plurality of adjacent memory cells during system mode.