Switch with one-bit resolution
First Claim
1. A method for implementing switching in a switch in a digital telecommunications system, in accordance with which methodN incoming signals are input to the switch, each comprising successive one-bit time slots that form successive frames, each frame comprising K time slots, the contents of the time slots for the incoming signals are stored in a memory (SM) at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location, one word at a time is read out from the memory (SM), wherefrom the desired bit is selected for the outbound signal from the switch, characterized in that the incoming signals are distributed to X multiplexers (A1 . . . Ax), each interleaving the incoming signals thereto into a single serial output signal (IN1 . . . INX), and writing into memory is carried out by writing the contents of the time slots of the output signals into the same memory location having a width of at least X bits, the memory location changing from one time slot of the output signals of the multiplexers to another.
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Abstract
The invention relates to implementing switching in a switch in a digital telecommunications system. N incoming signals are introduced to the switch, each comprising successive one-bit time slots that form successive frames each comprising K time slots. The contents of the time slots for the incoming signals are stored in a memory at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location. One word at a time is read out from the memory, wherefrom the desired bit is selected for the outbound signal from the switch. To optimize the size and power consumption of the switch, the incoming signals are distributed to X multiplexers (A1 . . . Ax), each interleaving the incoming signals thereto into a single serial output signal (IN1 . . . INX), and writing into memory is carried out by writing the contents of the time slots of the output signals into the same memory location having a width of at least X bits, the memory location changing from one time slot of the output signals of the multiplexers to another.
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Citations
9 Claims
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1. A method for implementing switching in a switch in a digital telecommunications system, in accordance with which method
N incoming signals are input to the switch, each comprising successive one-bit time slots that form successive frames, each frame comprising K time slots, the contents of the time slots for the incoming signals are stored in a memory (SM) at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location, one word at a time is read out from the memory (SM), wherefrom the desired bit is selected for the outbound signal from the switch, characterized in that the incoming signals are distributed to X multiplexers (A1 . . . Ax), each interleaving the incoming signals thereto into a single serial output signal (IN1 . . . INX), and writing into memory is carried out by writing the contents of the time slots of the output signals into the same memory location having a width of at least X bits, the memory location changing from one time slot of the output signals of the multiplexers to another.
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5. A switch for a digital telecommunications system for implementing switching with one bit resolution, said switch comprising
input connections for N incoming signals, each comprising successive one-bit time slots forming successive frames each comprising K time slots, a memory (SM) for storing the contents of the time lots for incoming signals at a memory location determined by a write address in such a way that a word having a length of several time slots is stored at one memory location, means (CM) for reading out one selected word at a time from said memory, and means (REG, SEL) for selecting a given bit from the word read out, characterized in that the switch further comprises X multiplexers (A1 . . . Ax) to which the incoming signals are connected in such a way that some of the signals arrive at each multiplexer, for interleaving the signals introduced to each multiplexer into a single serial output signal, and memory locations of a width of at least X bits in said memory (SM) for storing the contents of corresponding time slots of the output signals of the multiplexers at the same memory location.
Specification
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- Resources
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Current AssigneeNokia Solutions and Networks US LLC (Nokia Corporation)
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Original AssigneeNokia Telecommunications Oy (Nokia Corporation)
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InventorsKallioniemi, Tapio, Ruuskanen, Markku
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Primary Examiner(s)Chin, Wellington
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Assistant Examiner(s)Pham, Brenda H.
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Application NumberUS09/029,519Time in Patent Office1,118 DaysField of Search370/368, 370/369, 370/371, 370/372, 370/375, 370/376, 370/377, 370/378, 370/379, 370/381, 370/382, 370/383, 370/412US Class Current370/375CPC Class CodesH04Q 11/04 for time-division multiplex...
