Circuit for performing high-speed, low latency frame relay switching with support for fragmentation and reassembly and channel multiplexing

• US 6,208,650 B1
• Filed: 04/02/1998
• Issued: 03/27/2001
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Summit Technology Systems LP
• Original Assignee: Paradyne Corporation (Dasan Networks Incorporated)
• Inventors: McCabe, Patrick A., Villarosa, Louis F. Jr., Conner, Jeffrey E., Hassell, Suzanne
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US09/054,194
• Time in Patent Office: 1,090 Days
• Field of Search: 370/389, 370/392, 370/401, 370/410, 370/412, 370/428, 370/432, 370/463, 370/465, 370/469, 370/470, 370/471, 370/474, 370/522, 370/524, 370/535
• US Class Current: 370/392
• CPC Class Codes: H04L 49/251 Cut-through or wormhole routing
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

The present invention is a hardware implementation of frame relay switching functions which provides for real time concurrent multiple processes by implementing the processes in dedicated hardware logic operating in parallel, whereas in a typical software implementation the processes are sequentially processed. While data structures in software based implementations are accessed on some multiple of a byte regardless of the logical structure of the data, in the hardware implementation of the present invention the physical widths and the logical widths of the data structure elements are identical. This allows direct access of the logical structure by the operating process.

Claims

1. A circuit for switching frame-relay signals, said circuit comprising:

a receiving means for receiving high-level data link control (HDLC) signals, each HDLC signal having a header;

an input processing means for real-time concurrent multiple processing of the HDLC signals;

a storing means for storing the HDLC signals processed by said input processing means;

an output processing means for real-time concurrent multiple processing of the stored HDLC signals;

a transmitting means for transmitting the HDLC signals; and

an interfacing means for interfacing said receiving means, said input processing means, said storing means, said output processing means, and said transmitting means to a central processing unit (CPU).

2. The circuit of claim 1 wherein said circuit is an application specific integrated circuit (ASIC).

3. The circuit of claim 1, further comprising a CPU.

4. The circuit of claim 1, wherein said input processing means performs at least one of the following:

Extended Data Link Control Identifier (EDLCI) demultiplexing, Voice Over Frame Relay Implementation Agreement FRF.11 (FRF.11) demultiplexing, and Frame Relay Fragmentation Implementation Agreement FRF.12 (FRF.12) reassembly.

5. The circuit of claim 1, wherein said output processing means performs at least one of the following:

FRF.12 fragmentation, FRF.11 multiplexing, and EDLCI multiplexing.

6. The circuit of claim 1, further comprising a concentration highway (CHI) bus interface.

7. The circuit of claim 1 wherein said circuit switches a plurality of HDLC signals in parallel.

8. The circuit of claim 1, wherein said circuit switches a specific HDLC signal to a plurality of destinations.

9. The circuit of claim 1, wherein said circuit transmits the HDLC signals as soon as the header of each HDLC signal has been received and processed.

10. The circuit of claim 1, wherein said circuit transmits the HDLC signals in fragments.

11. The circuit of claim 1, wherein said circuit switches two or more HDLC signals.

12. The circuit of claim 11, further comprising a prioritizing means for performing priority resolution among said two or more HDLC signals.

13. An ASIC for switching frame-relay signals, the ASIC comprising:

a receiving means for receiving HDLC signals, each HDLC signal having a header;

an input processing means for real-time concurrent multiple processing of the HDLC signals;

a storing means for storing the HDLC signals processed by said input processing means;

an output processing means for real-time concurrent multiple processing of the stored HDLC signals;

a transmitting means for transmitting the HDLC signals; and

an interfacing means for interfacing said receiving means, said input processing means, said storing means, said output processing means, and said transmitting means to a CPU.

14. A circuit for switching frame-relay signals, said circuit comprising:

a first processing block comprising a receiving means for receiving HDLC signals having a header and a first processing means for real-time concurrent multiple processing of the HDLC signals;

a memory management block for managing the storage of the HDLC signals processed by said first processing means;

a second processing block comprising a second processing means for real-time concurrent multiple processing of the stored HDLC signals and a transmitting means for transmitting the stored HDLC signals after processing by said second processing means; and

an interface block for interfacing said first processing block, said memory management block, and said second processing block to a CPU.

15. The circuit of claim 14, wherein said circuit is implemented in an application specific integrated circuit (ASIC).

16. The circuit of claim 14, further comprising a CPU.

17. The circuit of claim 14, wherein said input processing means performs at least one of the following:

EDLCI demultiplexing, FRF.11 demultiplexing, and FRF.12 reassembly.

18. The circuit of claim 14, wherein said output processing means performs at least one of the following:

FRF.12 fragmentation, FRF.11 multiplexing, and EDLCI multiplexing.

19. The circuit of claim 14, wherein said memory management block further comprises interfacing means for interfacing said memory management block with a memory external to said circuit.

20. The circuit of claim 14, further comprising a dual concentration highway (CHI) bus interface.

21. The circuit of claim 14 wherein said circuit switches a plurality of HDLC signals in parallel.

22. The circuit of claim 14, wherein said circuit switches a specific HDLC signal to a plurality of destinations.

23. The circuit of claim 14, wherein said circuit transmits the HDLC signals as soon as the header of each HDLC signal has been received and processed.

24. The circuit of claim 14, wherein said circuit transmits the HDLC signals in fragments.

25. The circuit of claim 14, wherein said circuit switches two or more HDLC signals.

26. The circuit of claim 25, further comprising a prioritizing means for performing priority resolution among said two or more HDLC signals.

27. A method for switching frame-relay signals, comprising the steps of:

receiving, in an ASIC, HDLC signals, the HDLC signals having a header;

performing real-time concurrent multiple input processing on the HDLC signals in said ASIC;

storing the input processed HDLC signals;

performing real-time concurrent multiple output processing on the stored HDLC signals in said ASIC; and

transmitting the output processed HDLC signals from said ASIC.

28. The method of claim 27, wherein the input processing of said first performing step comprises at least one of the following:

EDLCI demultiplexing, FRF.11 demultiplexing, FRF.12 reassembly, and FRF.12 fragmentation.

29. The method of claim 27, wherein the output processing of said second performing step comprises at least one of the following:

FRF.12 fragmentation, FRF.11 multiplexing, and EDLCI multiplexing.

30. The method of claim 27, wherein said transmitting step transmits the output processed HDLC signals to a plurality of destinations.

31. The method of claim 27, wherein said transmitting step transmits the HDLC signals as soon as the header of each HDLC signal has been received and processed.

32. The method of claim 27, wherein said transmitting step transmits the HDLC signals in fragments.

33. A circuit for switching frame-relay signals, said circuit comprising:

a receiver configured to receive HDLC signals, each HDLC signal having a header;

an input processor configured to process real-time concurrent multiple HDLC signals;

a storage unit configured to store the HDLC signals processed by said input processing means;

an output processor configured to process real-time concurrent multiple HDLC signals;

a transmitter configured to transmit the HDLC signals; and

an interface configured to interface the receiver, the input processor, the buffer, the output processor, and the transmitter to a CPU.

34. The circuit of claim 33 wherein the circuit is an ASIC.

35. The circuit of claim 33, further comprising a CPU.

36. The circuit of claim 33, wherein the input processor performs at least one of the following:

Extended Data Link Control Identifier (EDLCI) demultiplexing, Voice Over Frame Relay Implementation Agreement FRF.11 (FRF.11) demultiplexing, and Frame Relay Fragmentation Implementation Agreement FRF.12 (FRF.12) reassembly.

37. The circuit of claim 33, wherein the output processor performs at least one of the following:

FRF.12 fragmentation, FRF.11 multiplexing, and EDLCI multiplexing.

38. The circuit of claim 33, further comprising a concentration highway CHI bus interface.

39. The circuit of claim 33 wherein the circuit switches a plurality of HDLC signals in parallel.

40. The circuit of claim 33, wherein the circuit switches a specific HDLC signal to a plurality of destinations.

41. The circuit of claim 33, wherein the circuit transmits HDLC signals as soon as the header of each HDLC signal has been received and processed.

42. The circuit of claim 33, wherein the circuit transmits HDLC signals in fragments.

43. The circuit of claim 33, wherein the circuit switches two or more HDLC signals.

44. The circuit of claim 43, further comprising a prioritizing unit configured to perform priority resolution among the two or more HDLC signals.

45. An ASIC configured to switch frame-relay signals, comprising:

a receiver configured to receive HDLC signals, each HDLC signal having a header;

an input processor configured to process real-time concurrent multiple HDLC signals;

a storage unit configured to store the HDLC signals processed by said input processing means;

an output processor configured to process real-time concurrent multiple HDLC signals;

a transmitter configured to transmit the HDLC signals; and

an interface configured to interface the receiver, the input processor, the buffer, the output processor, and the transmitter to a CPU.

46. A method for switching frame-relay signals, comprising the steps of:

receiving HDLC signals, each signal having a header;

performing real-time concurrent multiple input processing on the HDLC signals;

storing the input processed HDLC signals;

performing real-time concurrent multiple output processing on the stored HDLC signals; and

transmitting the output processed HDLC signals.

47. The method of claim 46, wherein the input processing of the first performing step comprises at least one of the following:

EDLCI demultiplexing, FRF.11 demultiplexing, FRF.12 reassembly, and FRF.12 fragmentation.

48. The method of claim 46, wherein the output processing of the second performing step comprises at least one of the following:

FRF.12 fragmentation, FRF.11 multiplexing, and EDLCI multiplexing.

49. The method of claim 46, wherein the transmitting step transmits the output processed HDLC signals to a plurality of destinations.

50. The method of claim 46, wherein the transmitting step transmits the HDLC signals as soon as the header of each HDLC signal has been received and processed.

51. The method of claim 46, wherein the transmitting step transmits the HDLC signals in fragments.