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Circuit for performing high-speed, low latency frame relay switching with support for fragmentation and reassembly and channel multiplexing

  • US 6,208,650 B1
  • Filed: 04/02/1998
  • Issued: 03/27/2001
  • Est. Priority Date: 12/30/1997
  • Status: Expired due to Fees
First Claim
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1. A circuit for switching frame-relay signals, said circuit comprising:

  • a receiving means for receiving high-level data link control (HDLC) signals, each HDLC signal having a header;

    an input processing means for real-time concurrent multiple processing of the HDLC signals;

    a storing means for storing the HDLC signals processed by said input processing means;

    an output processing means for real-time concurrent multiple processing of the stored HDLC signals;

    a transmitting means for transmitting the HDLC signals; and

    an interfacing means for interfacing said receiving means, said input processing means, said storing means, said output processing means, and said transmitting means to a central processing unit (CPU).

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