Data processing system for logically adjacent data samples such as image data in a machine vision system

• US 6,208,772 B1
• Filed: 10/17/1997
• Issued: 03/27/2001
• Est. Priority Date: 10/17/1997
• Status: Expired due to Term

• Current Assignee: Microscan Systems Inc (Omron Corporation)
• Original Assignee: Acuity Brands, Inc.
• Inventors: Wilt, Michael John, Greenberg, Michael Philip
• Primary Examiner(s): Au, Amelia
• Assistant Examiner(s): Wu, Jingge
• Application Number:
  US08/953,772
• Time in Patent Office: 1,257 Days
• Field of Search: 382/205, 382/300, 382/307, 382/308, 382/303, 382/304, 382/305, 345/503, 395/800.22, 395/800.32, 395/800.33, 395/800.34, 395/800.35, 395/800.36
• US Class Current: 382/308
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 3/4007 based on interpolation, e.g. bilinear interpolation image demosaicing G06T3/4015; edge-driven or edge-based scaling G06T3/403
• CPC Class Codes: G06T 5/20 using local operators

Abstract

A data processing system including a data processor, also called a processing accelerator, processes at least one processor word each clock cycle. Each processor word includes multiple complete data samples which are received individually as part of a sequential stream of logically adjacent or related data samples such as in image data pixels which are part of an image to be processed by a machine vision system. A predetermined number of the data samples are stored together, as a processor word, in dedicated processing accelerator memory. For example, four 8 bit data samples can be stored together as one 32 bit processor word. The system also includes a data aligner which allows the processing accelerator to process at least one processor word comprised of at least one data sample from two processor words. The aligner controls data sample alignment such as for example, pixel alignment in the case of a vision system, to facilitate image data processing. Various processing units are also disclosed including: a neighborhood formation processing unit which, in a vision system, allows the processing accelerator to evaluate and process data within a neighborhood of one or more particular data elements, such as a pixel.

Claims

1. A data processing system, comprising:

a data organizer, for receiving a sequential stream of data comprising a plurality of logically adjacent data samples, and for organizing a digital representation of a predetermined number of said plurality of logically adjacent data samples into a processor word;

at least one data sample memory, responsive to said data organizer, for storing a plurality of said processor words;

a data word aligner, responsive to said at least one data sample memory, for receiving at least first and second said processor words, for selecting at least one data sample from said first processor word and at least one data sample from said second processor word, and for providing at least one aligned processor word comprising said predetermined number of said plurality of logically adjacent data samples, said aligned processor word including at least said selected at least one data sample from said first processor word and said selected at least one data sample from said second processor word; and

at least one word-wide data processor, responsive to said data word aligner, for receiving a sequential stream of said aligned processor words, each said aligned processor word comprising said predetermined number of said logically adjacent data samples, for simultaneously processing said predetermined number of logically adjacent data samples received as said sequential stream of aligned processor words, and for generating a sequential stream of data processor result words based on said simultaneously processed predetermined number of logically adjacent data samples received as said one aligned processor word from said sequential stream of aligned processor words, said at least one word-wide data processor selected from the group consisting of;

a neighborhood processing unit;

an image arithmetic processing unit;

a segmentation processing unit;

a morphology processing unit; and

a correlation processing unit.

2. The processing system of claim 1 wherein said logically adjacent data samples include image data, each of said plurality of logically adjacent image data samples representing one pixel of image data from an image to be processed, wherein logically adjacent sequential image data samples represent adjacent pixels of image data from said image to be processed, and wherein said data sample memory stores at least two adjacent pixels of image data together as one said processor word.

3. The processing system of claim 2 wherein said data sample memory transfers and said word-wide data processor receives at least one processor word each processor cycle.

4. The processing system of claim 1 further including a memory address generator, coupled to said at least one data memory, for addressing said memory to provide said at least first and second processor words.

5. The processing system of claim 2 wherein said neighborhood processing unit includes a neighborhood image processing unit, for forming at least two neighborhoods of predetermined size around at least two pixels of image data.

6. The processing system of claim 2 wherein said neighborhood processing unit includes a neighborhood image processing unit, for forming at least two neighborhoods of predetermined size around each of said at least two adjacent pixels of image data stored together as said processor word.

7. The processing system of claim 1 wherein said word-wide data processor is coupled to a data bus, said data bus for transporting processor words from said data organizer to a primary data sample target device;

and

wherein said word-wide data processor further includes a data capture device, for controlling the simultaneous capture of processor words being transmitted over said data bus to said primary data sample target, and for storing a copy of said processor words in said at least one data sample memory.

8. The processing system of claim 1 wherein said at least one data sample memory includes first and second data sample memories;

and

further including at least one processing sequencer, for reading instructions and processor register values from said at least one data sample memory, and for writing at least processor register values to at least said at least one data sample memory.

9. The processing system of claim 1 further including at least one data sample memory controller, for executing data sample memory control instructions while said at least one data sample memory is providing sequential data sample values as processor words.

10. The processing system of claim 1, wherein said word-wide sample data processor further includes at least one word-wide sample data processing unit.

11. The processing system of claim 10, wherein said at least one word-wide sample data processing unit is selected from the group consisting of:

a neighborhood processing unit;

an arithmetic processing unit;

a segmentation processing unit;

a morphology processing unit; and

a correlation processing unit.

13. The processing system of claim 2, wherein said at least one data sample memory includes at least one burst-mode data sample memory including a two-dimensional array of sample registers connected so complete processor words flow through said array and complete neighborhoods of image data sample values surrounding each pixel of image data may be simultaneously extracted from said array for simultaneous processing.

14. The processing system of claim 1, wherein said data organizer is coupled to a data bus, said data bus for transporting data from said data organizer to a primary data sample target device;

and wherein said data processor further includes a data capture device for controlling the simultaneous capture of data samples being transmitted over said data bus to said primary sample data target, and for storing a copy of said data samples in said at least one burst-mode data sample memory.

15. The processing system of claim 1 further including at least one processing sequencer for reading instructions from said at least one data sample memory and for writing at least processor register values to at least one data sample memory.

16. The processing system of claim 1 further including at least one data sample memory controller, for executing data sample memory control instructions while said at least one data sample memory is providing sequential data sample values as processor words.

12. The processing unit of clam 1 further comprising a word-wide neighborhood processing image processing unit, for simultaneously forming and processing at least two neighborhoods of predetermined size around at least two pixels of image data.