Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture

• US 6,208,947 B1
• Filed: 03/29/2000
• Issued: 03/27/2001
• Est. Priority Date: 02/26/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J.
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US09/537,839
• Time in Patent Office: 363 Days
• Field of Search: 702/118, 702/117, 702/120, 702/182, 702/81, 702/82, 702/83, 702/84, 700/95, 700/109, 700/115, 700/116, 700/117, 700/224, 700/226, 438/5, 438/14, 438/10, 438/16, 438/17
• US Class Current: 702/118
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inventive method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating IC'"'"'s on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad IC'"'"'s on the wafer and the fuse ID'"'"'s of the IC'"'"'s on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad IC'"'"'s that have accidentally been assembled into IC devices. These “bad” IC devices are discarded, and the remaining IC devices continue on to back-end testing.

Claims

1. A manufacturing process for redirecting one or more integrated circuit devices that have been identified as having undergone a process flow within the manufacturing process different from the process flow of their stored data, each integrated circuit device having a substantially unique identification code, the process comprising:

storing data and the identification code of said each integrated circuit device of the one or more integrated circuit devices, said data indicating a process flow within the manufacturing process for each integrated circuit device of the integrated circuit devices;

reading the identification code of each integrated circuit device of the integrated circuit devices;

accessing the data stored and the identification code of said each integrated circuit device of the one or more integrated circuit devices;

evaluating the data accessed for said each integrated circuit device of the one or more integrated circuit devices;

identifying integrated circuit devices having undergone a process flow within the manufacturing process different from the process flow of their stored data; and

redirecting said each integrated circuit device of the one or more integrated circuit devices identified as having undergone a process flow within the manufacturing process different from the process flow of their stored data.

2. The process of claim 1, wherein storing data comprises storing the identification code of said each of the integrated circuit devices of the one or more integrated circuit devices and a die location on an electronically stored wafer map.

3. The process of claim 1, wherein said storing data comprises storing data at a probe.

4. The process of claim 1, wherein said storing data comprises storing data and the identification code of said each integrated circuit device of the one or more integrated circuit devices to indicate said each integrated circuit device of the one or more integrated circuit devices is one of a good integrated circuit device usable for assembly and back-end testing and a bad integrated circuit device suitable for being discarded.

5. The process of claim 1, wherein said reading the identification code of said each integrated circuit device of the one or more integrated circuit devices comprises electrically retrieving a unique fuse identification programmed into said each integrated circuit device of the one or more integrated circuit devices.

6. The process of claim 1, wherein said reading the identification code of said each integrated circuit device of the one or more integrated circuit devices comprises optically reading a unique identification code provided on said each integrated circuit device of the one or more integrated circuit devices.

7. The process of claim 6, wherein said optically reading the unique identification code provided on said each integrated circuit device of the one or more integrated circuit devices comprises optically reading a unique laser fuse identification programmed into said each integrated circuit device of the one or more integrated circuit devices.

8. The process of claim 1, wherein said reading the identification code of said each integrated circuit device of the one or more integrated circuit devices comprises reading the identification code of said each integrated circuit device of the one or more integrated circuit devices at an opens/shorts test in the manufacturing process.

9. The process of claim 1, wherein said accessing the data stored and the identification code of said each integrated circuit device of the one or more integrated circuit devices comprises accessing the data stored and the identification code of said each integrated circuit device of the one or more integrated circuit devices at an opens/shorts test in the manufacturing process.

10. The process of claim 1, wherein said evaluating the data comprises evaluating the data accessed for said each integrated circuit device of the one or more integrated circuit devices to identify any bad integrated circuit devices having undergone an assembly procedure within the manufacturing process.

11. The process of claim 1, wherein said evaluating the data comprises evaluating the data at an opens/shorts test in the manufacturing process.

12. The process of claim 1, wherein said redirecting any integrated circuit device identified as having been mis-processed comprises discarding any integrated circuit device identified as having been mis-processed.

13. The process of claim 1, wherein said redirecting occurs before a back-end test procedure within the integrated circuit device manufacturing process.

14. The process of claim 1, further comprising assembling the integrated circuit devices into packaged integrated circuit devices after storing data and before reading the identification code of said each of the integrated circuit devices of the one or more integrated circuit devices.

15. A method of manufacturing integrated circuit devices from semiconductor wafers, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of integrated circuit devices on each wafer of the plurality of semiconductor wafers;

causing each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to store a substantially unique identification code;

storing data and the identification code of said each integrated circuit device of the plurality of integrated circuit devices indicating a manufacturing process flow for said each integrated circuit device of the plurality of integrated circuit devices;

separating each integrated circuit device of the integrated circuit devices on each wafer of the plurality of semiconductor wafers to form an integrated circuit device of a plurality of integrated circuit devices;

assembling said each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device assembly;

reading the identification code of said each integrated circuit device of the integrated circuit device assemblies;

accessing the data stored and the identification code associated with said each integrated circuit device of the integrated circuit device assemblies;

evaluating the data accessed for said each integrated circuit device of the integrated circuit device assemblies identifying any integrated circuit devices having undergone a manufacturing process flow different from the indicated manufacturing process flow of their stored data;

subjecting to further processing an integrated circuit device identified as having undergone a manufacturing process flow different from the indicated manufacturing process flow of its stored data; and

back-end testing integrated circuit devices not subjected to further processing.

16. The method of claim 15, wherein said fabricating a plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers comprises fabricating integrated circuit devices selected from a group comprising Dynamic Random Access Memory (DRAM) devices, Static Random Access Memory (SRAM) devices, Synchronous DRAM (SDRAM) devices, and processor devices.

17. The method of claim 15, wherein said causing said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to store a substantially unique identification code comprises programming said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to permanently store a unique fuse identification.

18. The method of claim 17, wherein said programming said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to permanently store the unique fuse identification comprises programming at least one of the fuses and anti-fuses in said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to permanently store the unique fuse identification.

19. The method of claim 15, wherein said assembling said each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device comprises:

picking each integrated circuit device of the plurality of integrated circuit devices from its wafer;

placing said each integrated circuit device of the plurality of integrated circuit devices onto an epoxy coated bonding site of one of a plurality of lead frames;

curing the epoxy on the bonding site of each one of plurality of the lead frames;

wire bonding said each integrated circuit device of the plurality of integrated circuit devices to its associated lead frame;

injection molding said each integrated circuit device of the plurality of integrated circuit devices and the associated lead frame to form one of a plurality of integrated circuit device packages, each having projecting leads;

de-flashing the projecting leads of each integrated circuit device package of the plurality of integrated circuit device packages;

curing said each integrated circuit device package of the plurality of integrated circuit device packages;

electroplating the projecting leads of said each integrated circuit device package of the plurality of integrated circuit device packages;

singulating said each integrated circuit device package of the plurality of integrated circuit device packages into one of a plurality of discrete integrated circuit devices; and

testing said each integrated circuit device of the plurality of integrated circuit devices for opens and shorts.

20. The method of claim 15, wherein said assembling said each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device comprises assembling said each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device selected from a group comprising a wire bond/lead frame integrated circuit device, a Chip-On-Board (COB) integrated circuit device, a flip-chip integrated circuit device, and a Tape-Automated Bonding (TAB) integrated circuit device.

21. A method of manufacturing Multi-Chip Modules from semiconductor wafers, the method comprising:

providing a plurality of integrated circuit devices on each wafer of a plurality of semiconductor wafers;

causing each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to store a substantially unique identification code;

storing data and the identification code of said each integrated circuit device of the plurality of integrated circuit devices indicating a desired manufacturing process flow for said each integrated circuit device of the plurality of integrated circuit devices;

separating said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers from the wafer to form one of a plurality of integrated circuit devices;

assembling one or more integrated circuit devices of the plurality of integrated circuit devices into each of a plurality of multi-chip modules;

reading the identification code of said each integrated circuit device of the plurality of integrated circuit devices in said each of the plurality of multi-chip modules;

accessing the data stored and the identification code of said each integrated circuit device of the plurality of integrated circuit devices in said each of the plurality of multi-chip modules;

evaluating the data accessed for said each integrated circuit device of the plurality of integrated circuit devices in said each of the plurality of multi-chip modules identifying any multi-chip modules having integrated circuit devices having undergone a manufacturing process flow that is different from the desired manufacturing process flow;

redirecting any multi-chip modules identified as having integrated circuit devices having undergone a manufacturing process flow that is different from the desired manufacturing process flow; and

back-end testing any non-redirected multi-chip modules.

22. The method of claim 21, wherein the plurality of multi-chip modules are selected from a group comprising Single In-Line Memory Modules (SIMM'"'"'s) and Dual In-line Memory Modules (DIMM'"'"'s).

23. A method of manufacturing integrated circuit devices from semiconductor wafers the method comprising:

providing a plurality of integrated circuit devices on each wafer of a plurality of semiconductor wafers;

electronically probing each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to identify good and defective integrated circuit devices on said each wafer of the plurality of semiconductor wafers;

programming said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers to store a unique fuse identification;

storing an electronic wafer map for said each wafer of the plurality of semiconductor wafers that identifies locations of good and defective integrated circuit devices on the wafer associating each integrated circuit device on the wafer with its fuse identification;

sawing said each integrated circuit device of the plurality of integrated circuit devices on said each wafer of the plurality of semiconductor wafers from its wafer to form one of a plurality of discrete integrated circuit devices;

automatically picking said each integrated circuit device of the plurality of integrated circuit devices from the wafer;

placing said each integrated circuit device of the plurality of integrated circuit devices onto an epoxy coated bonding site of one of a plurality of lead frames;

curing the epoxy on the bonding site of said each lead frame of the plurality of lead frames;

wire bonding said each integrated circuit device of the plurality of integrated circuit devices to an associated lead frame;

injection molding said each integrated circuit device of the plurality of integrated circuit devices and the associated lead frame forming one of a plurality of integrated circuit device packages, each package having projecting leads;

de-flashing the projecting leads of said each integrated circuit device package of the plurality of integrated circuit device packages;

curing said each integrated circuit device package of the plurality of integrated circuit device packages;

electroplating the projecting leads of said each integrated circuit device package of the plurality of integrated circuit device packages;

singulating said each integrated circuit device package of the plurality of integrated circuit device packages into one of a plurality of discrete integrated circuit devices;

testing said each integrated circuit device of the plurality of integrated circuit devices for opens and shorts;

electrically retrieving the fuse identification associated with said each integrated circuit device of the plurality of integrated circuit devices;

accessing the wafer map stored in association with the fuse identification associated with each integrated circuit device of the plurality of integrated circuit devices;

evaluating the wafer map accessed for said each integrated circuit device of the plurality of integrated circuit devices identifying any defective integrated circuit device and any good integrated circuit device;

discarding any integrated circuit device identified as a defective integrated circuit device; and

back-end testing any integrated circuit device identified as a good integrated circuit device.