Method for scheduling event sequences

• US 6,208,954 B1
• Filed: 09/16/1994
• Issued: 03/27/2001
• Est. Priority Date: 09/16/1994
• Status: Expired due to Term

• Current Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Original Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Inventors: Houtchens, Steven P.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/307,178
• Time in Patent Office: 2,384 Days
• Field of Search: 364/578, 364/228.3, 364/229.3, 364/232.3, 364/270, 364/DIG.1, 395/500, 395/800, 703/16, 703/17, 703/20, 703/26
• US Class Current: 703/16
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus for sequencing the execution of a simulation system comprising at least two subsystem simulators. The simulation system further comprises a first and second simulator, a processor for executing program instructions of a control program stored in a memory coupled to the processor, a router for coupling first simulator inputs and outputs to second simulator outputs and inputs respectively, and an input device including a control and monitor panel for controlling said sequencing. The control program controls a plurality of subsystem simulators and comprises an initiation sequence for initiating execution of a first simulator at an initiation time including defining a first simulator output state, a first execution sequence wherein said first simulator executes a simulation and updates first simulator outputs to said second simulator, a first halt sequence for halting said first execution sequence, a first transfer sequence for transferring first simulator output data to said second simulator inputs, a second execution sequence wherein said second simulator executes a simulation after said first simulator execution has halted, a second halt sequence for halting said second execution sequence at a second halt time equal to the earlier of said first halt time and a change in state of said second simulator outputs, a repeat sequence for restarting said first execution sequence to run until a final simulation time is reached, and a back-up sequence for restarting the first execution sequence at a last verified simulation time.

Claims

1. A method for scheduling processes of a first simulator and a second simulator, the simulators having cross coupled first and second simulator inputs and outputs, the method being executed by at least one processor pursuant to program instructions of a control program stored in a memory coupled to said at least one processor, the first and second simulators stored as first and second simulation programs, respectively, in said memory and executed by said at least one processor, the method including the steps of:

(1) define an initial state, whereby said first and second simulator outputs are initialized and a verified simulation time (vt) and a first simulator current simulation time (ct₁) are set to an initial time value (t₀);

(2) select and store a target timepoint (tt) later than said first simulator current simulation time (ct₁);

(3) begin execution of said first simulator program using said second simulator outputs as initial first simulator inputs;

(4) update said first simulator outputs by a first step time (Δ

t₁) not greater than said target timepoint (tt);

(5) define a second state, whereby said updated first simulator outputs do not equal said first simulator outputs;

(6) define a third state whereby said updated first simulator outputs equal said first simulator outputs;

(7) when said second state occurs store the simulation time at which said first simulator outputs changed as new target timepoint (tt);

(8) when said third state occurs continue updating said first simulator outputs stepwise at step (4) until said first simulator currnt simulation time (ct₁) equals said target timepint (tt);

(9) post said updated first simulator outputs and target timepoint (tt) as new second simulator inputs to said second simulator and store a state of said first simulator;

(10) begin execution of said second simulator program using said second simulator inputs, with said verified simulation time (vt) as a current simulation time (ct₂) for said second simulator;

(11) update said second simulator outputs by a second step time (Δ

t₂) not greater thnm said target timepoint (tt);

(12) define a fourth state, whereby said updated second simulator outputs do not equal said second simulator outputs;

(13) when said fourth state occurs,

a) store a simulation time at which the second simulator outputs changed as a new target timepoint (tt),

b) post said changed second simulator outputs and said new target timepoint as new first simulator inputs to said first simulator,

c) back up said first simulator to said verified simulation time (vt),

d) generate new values for said first simulator outputs using said new first simulator inputs and said new target timepoint as an ending time for the simulation,

e) store said new target timepoint as said verified simulation time and as said first simulator current simulation time (ct₁), and

f) continue until said verified simulation time equals a simulation completion time by proceeding to step 2;

(14) continue updating said second simulator outputs stepwise until said second simulator current simulation time (ct₂) equals said target timepoint (tt);

(15) store said new target timepoint as said verified simulation time and as said first simulator current simulation time (ct₁); and

(16) continue until said verified simulation time equals a simulation completion time by proceeding to step 2.

2. A method for scheduling processes of a first simulator and a second simulator, said simulators having cross coupled first and second simulator inputs and outputs, the method being executed by at least one processor pursuant to program instructions of a control program stored in a memory coupled to said at least one processor, said first and second simulator processes stored as first and second simulation programs, respectively, in said memory and executed by said at least one processor, the method including the steps of:

(1) define an initial state, whereby said first and second simulator outputs are initialized and coupled to said second and first simulator inputs respectively, and a verified simulation time (vt) and a first simulator current simulation time (ct₁) are set to an initial time value (t₀);

(2) select and store a target timepoint (tt) later than said first simulatuo current simulation time (ct₁);

(3) begin execution of said first simulator program using said second simulator outputs as first simulator inputs;

(4) update said first simulator outputs for said target timepoint (tt);

(5) post said updated first simulator outputs and target timepoint (tt) as new second simulator inputs to said second simulator and store a state of said first simulator;

(6) begin execution of said second simulator program using said new second simulator inputs, with said verified simulation time (vt) as a second simulator current simulation time (ct₂) for said second simulator process;

(7) update said second simulator outputs by a first step time (Δ

t₁) not greater than said target timepoint (tt);

(8) define a second state, whereby said updated second simulator outputs do not equal said initialized second simulator outputs;

(9) when said second state occurs,

a) store a simulation time at which said second simulator outputs changed as a new target timepoint (tt),

b) post said changed second simulator outputs and said new target timepoint (tt) as new first simulator inputs to said first simulator,

c) back up said first simulator to said verified simulation time (vt),

d) generate new values for said first simulator outputs using said new first simulator inputs and said new target timepoint as an ending time for the simulation,

e) store said new target timepoint as said verified simulation time (vt) and as said first simulator current simulation time (ct₁), and

f) continue until said verified simulation time equals a simulation completion time by proceeding to step 2;

(10) continue updating said second simulator outputs stepwise at step 7 until said second simulator current simulation time (ct₂) equals said target timepoint (tt);

(11) store said target timepoint as said verified simulation time and as said first simulator current simulation time (ct₁); and

(12) continue until said verified simulation time equals said simulation completion time by proceeding to step 2.

3. A method for scheduling processes of a first simulator and a second simulator, said simulators having cross coupled first and second simulator inputs and outputs, the method being executed by at least one processor pursuant to program instructions of a control program stored in a memory coupled to said at least one processor, the first and second simulator processes stored as first and second simulation programs, respectively, in said memory and executed by said at least one processor, the method including the steps of:

(1) define an initial state, whereby said first and second simulator outputs are coupled to said first and second simulator inputs and a verified simulation time (vt) and a first simulator current simulation time (ct₁) are set to an initial time value (t₀);

(2) select and store a target timepoint (tt) later than said first simulator current simulation time (ct₁);

(3) begin execution of said first simulator program using said first simulator inputs;

(4) update said first simulator outputs for said target timepoint (tt);

(5) define a second state, whereby said updated first simulator outputs do not equal said initialized first simulator outputs;

(6) when said second state occurs, post said updated first simulator outputs and target timepoint (tt) as new second simulator inputs to said second simulator and store a state of said first simulator;

(7) begin execution of said second simulator program using said second simulator inputs, with said verified simulation time (vt) as a second simulator current simulation time (ct₂) for said second simulator;

(8) update said second simulator outputs for said target timepoint (tt);

(9) define a third state wherein said updated second simulator outputs have changed relative to said second simulator outputs as calculated at a most recent preceding time of calculation;

(10) when said third state occurs

(a) post said changed second simulator outputs and target timepoint as new first simulator inputs to said first simulator;

(b) back up said first simulator to said verified simulation time,

(c) generate new values for said first simulator outputs using said new first simulator inputs and said target timepoint as an ending time for the simulation,

(d) store said target timepoint as said verified simulation time and as said first simulator current simulation time, and

(e) continue at step 2 until a final simulation time is reached; and

(11) store said target timepoint as said verified simulation time and continue at step 2 until said final simulation time is reached.

4. A method for scheduling processes of a first simulator and a second simulator, said simulators having first simulator inputs and second simulator inputs, respectively, the method being executed by at least one processor pursuant to program instructions of a program stored in a memory coupled to said at least one processor, said first and second simulators being implemented as first and second simulation programs, respectively, stored in said memory and executed by said at least one processor, the method including the steps of:

(1) generating initial first simulator outputs based upon said first simulator inputs and initial second simulator outputs based upon said second simulator inputs;

(2) storing an initial time value as a value for both a verified simulation time and a current simulation time, and storing a target timepoint;

(3) beginning execution of said first simulator using said first simulator inputs, with said verified simulation time as a beginning time for the simulation;

(4) generating new first simulator outputs by said first simulator using a simulation time later than said current simulation time by an amount equal to a predetermined first time step not greater than said target timepoint (tt);

(5) when said first simulator outputs have changed relative to said first simulator outputs as calculated at a most recent preceding time of calculation, storing a simulation time at which said first simulator outputs changed as said target timepoint, storing a state of said first simulator and posting said changed first simulator outputs and said target timepoint to said second simulator;

(6) beginning execution of said second simulator using said second simulator inputs, with said verified simulation time as said current simulation time;

(7) generating new second simulator outputs by said second simulator using a simulation time later than said current simulation time by an amount equal to a predetermined second time step not greater than said target timepoint (tt);

(8) when said second simulator outputs have changed relative to said second simulator outputs as calculated at a most recent preceding time of calculation, then storing a simulation time at which said second simulator outputs changed as said target timepoint, and posting said changed second simulator outputs and said target timepoint as new first simulator inputs to said first simulator;

(9) when said target timepoint value has changed in step 8, then

(a) backing up said first simulator to said verified simulation time,

(b) generating new values for said first simulator outputs using said new first simulator inputs and said target timepoint as an ending time for the simulation,

(c) storing said target timepoint as said verified simulation time and as said current simulation time,

(d) posting said current simulation time, said verified simulation time and said first simulator output values as new second simulator inputs to said second simulator, and

(e) proceeding to step 3;

(10) continuing stepwise at step 7 until said target timepoint is reached and then storing said target timepoint as said verified simulation time and as said current simulation time; and

(11) repeating steps 3 through 10 until a predetermined final simulation time is reached.

5. A system for sequencing an execution of a plurality of subsystem simulators comprising:

(1) at least one central processing units (CPU) including a microprocessor coupled to a memory element for storing a control program, said CPU coupled to an input device for controlling said sequencing, said input device comprising a control and monitor panel for initiating and terminating said sequencing;

(2) a first simulator, said first simulator comprising inputs and outputs;

(3) a second simulator, said second simulator comprising inputs and outputs;

(4) a router for coupling said first simulator inputs and outputs to said second simulator outputs and inputs respectively; and

(5) said control program comprising

(a) an initiation sequence for initiating execution of said first simulator at an initiation time including defining a first simulator output state,

(b) a first execution sequence wherein said first simulator executes a simulation and updates said first simulator outputs,

(c) a first halt sequence for halting said first execution sequence at a first halt time, equal to the earlier of a predetermined time and when said first simulator outputs change states, and for storing a state of said first simulator at said first halt time,

(d) a first transfer sequence for transferring said first simulator outputs to said second simulator inputs,

(e) a second execution sequence wherein said second simulator executes a simulation after said first simulator execution has halted,

(f) a second halt sequence for halting said second execution sequence at a second halt time equal to the earlier of said first halt time and when said second simulator outputs change state,

(g) a second transfer sequence for transferring said second simulator outputs including said second halt time to said first simulator inputs,

(h) a repeat sequence for setting said initiation time equal to said second halt time and restarting said first execution sequence to run at said second halt time until a final simulation time is reached, and

(i) a back-up sequence for establishing a verified simulation time wherein said first execution sequence is restarted at a time prior to said second halt time upon said change in state of said second simulator outputs.

6. The sequencing system of claim 5 wherein said time prior to said second halt time is a last verified simulation time, said last verified simulation equal to said initiation time.

7. The sequencing system of claim 5 wherein said first execution sequence further comprises updating said first simulator outputs at a plurality of time intervals between said initiation time and said predetermined time until said first simulator outputs change state.

8. The sequencing system of claim 5 wherein said first transfer sequence transfers first simulator outputs including said first halt time to said second simulator inputs.

9. The sequencing system of claim 5 wherein said second execution sequence further comprises updating said second simulator outputs at a plurality of time intervals between said initiation time and said first halt time until said second simulator outputs change state.

10. The sequencing system of claim 5 wherein said second transfer sequence transfers said second simulator outputs including said second halt time to said first simulator inputs.

11. A method for sequencing an execution of a simulation system comprising at least two subsystem simulators, said simulation system further comprising a first and second simulator having first simulator inputs and second simulator inputs, respectively, the method being executed by at least one processor pursuant to program instructions of a program stored in a memory coupled to said at least one processor, said first and second simulators being implemented as first and second simulation programs, respectively, stored in said memory and executed by said at least one processor, the method comprising the steps of:

(a) initiating execution of said first simulator at an initiation time including defining a first simulator output state;

(b) executing a first execution sequence wherein said first simulator performs a simulation and updates said first simulator outputs to said second simulator;

(c) halting said first execution sequence at a first halt time, equal to the earlier of a predetermined time and when a state of said first simulator outputs change, and storing a state of said first simulator;

(d) transferring said first simulator outputs to said second simulator inputs;

(e) executing a second execution sequence wherein said second simulator performs a simulation after said first simulator execution sequence has halted;

(f) halting said second execution sequence at a second halt time equal to the earlier of said first halt time and a change in state of said second simulator outputs;

(g) transferring said second simulator outputs including second halt time to said first simulator inputs;

(h) setting said initiation time equal to said second halt time and restarting said first execution sequence to run at said second halt time until a final simulation time is reached; and

(i) executing a back-up sequence for establishing a verified simulation time wherein said first execution sequence is restarted at a time prior to said second halt time upon said change in state of said second simulator outputs.

12. The sequencing method of claim 11 wherein said time prior to said second halt time is a last verified simulation time, said last verified simulation equal to said initiation time.

13. The sequencing method of claim 11 wherein said first execution sequence further comprises updating said first simulator outputs at a plurality of time intervals between said initiation time and said predetermined time until said first simulator outputs change state.

14. The sequencing method of claim 11 wherein said transferring first simulator outputs step transfers said first simulator outputs including said first halt time to said second simulator inputs.

15. The sequencing system of claim 11 wherein said second execution sequence further comprises updating said second simulator outputs at a plurality of time intervals between said initiation time and said first halt time until said second simulator outputs change state.

16. The sequencing system of claim 11 wherein said transferring second simulator outputs step transfers said second simulator outputs including said second halt time to said first simulator inputs.

17. A method for scheduling processes of a first simulator and a second simulator, said simulators having first simulator inputs and outputs and second simulator inputs and outputs, respectively, the method being executed by at least one processor pursuant to program instructions of a control program stored in a memory coupled to said at least one processor, said first and second simulators stored as first and second simulation programs, respectively, in said memory and executed by said at least one processor, the method including the steps of:

(1) initialize said first and second simulator outputs;

(2) store an initial time value as a value for both a verified simulation time (vt) and as a first simulator current simulation time (ct₁);

(3) store a target timepoint (tt) later than said first simulator current simulation time (ct₁) and begin execution of said first simulator program using said second simulator outputs as first simulator inputs;

(4) update said first simulator outputs for said target timepoint (tt);

(5) when said updated first simulator outputs do not equal said initialized first simulator outputs, post said updated first simulator outputs and said target timepoint as new second simulator inputs to said second simulator and store a state of said first simulator;

(6) begin execution of said second simulator program using said second simulator inputs, with said verified simulation time as a second simulator current simulation time;

(7) generate new second simulator outputs by said second simulator using a simulation time later than said first simulator current simulation time by an amount equal to a predetermined first time step not greater than said target timepoint (tt);

(8) when said second simulator outputs have changed relative to said second simulator outputs as calculated at a most recent preceding time of calculation,

(a) stop said second simulator program,

(b) store a simulation time at which said second simulator outputs changed as said target timepoint (tt), and post said changed second simulator outputs and said target timepoint as new first simulator inputs to said first simulator,

(c) back up said first simulator to said verified simulation time,

(d) using said new first simulator inputs to generate new values for said first simulator outputs using said target timepoint as an ending time for the simulation,

(e) store said target timepoint as said verified simulation time and as said current simulation time,

(f) post said first simulator current simulation time, said verified simulation time and said first simulator outputs as new second simulator inputs to said second simulator, and

(g) continue at step 3 until a predetermined final simulation time is reached;

(9) stop said second simulator program at said target timepoint (tt);

(10) post said target timepoint and said second simulator outputs as new first simulator inputs to said first simulator;

(11) update said verified simulation time to said target timepoint (tt); and

(12) continue at step 3 until said predetermined final simulation time is reached.

18. A method for scheduling processes of a first simulator and a second simulator, said simulators having first simulator inputs and outputs and second simulator inputs and outputs, respectively, the method being executed by at least one processor pursuant to program instructions of a control program stored in a memory coupled to said at least one processor, said first and second simulators stored as first and second simulation programs, respectively, in said memory and executed by said at least one processor, the method including the steps of:

(1) initialize said first and second simulator outputs;

(2) store an initial time value (t₀) as a value for both a verified simulation time (vt) and as a first simulator current simulation time (ct₁);

(3) store a target timepoint (tt) later than said first simulator current simulation time (ct₁) and begin execution of said first simulator program using said second simulator outputs as first simulator inputs;

(4) update said first simulator outputs for said target timepoint (tt);

(5) when said updated first simulator outputs do not equal said initialized first simulator outputs, post said updated first simulator outputs and target timepoint as new second simlulator inputs to said second simulator and store a state of said first simulator;

(6) begin execution of said second simulator program using said second simulator inputs, with said verified simulation time as a second simulator current simulation time;

(7) generate new second simulator outputs by said second simulator for said target timepoint (tt);

(8) when said second simulator outputs have changed relative to said second simulator outputs as calculated at a most recent preceding time of calculation,

(a) stop said second simulator program,

(b) post said changed second simulator outputs and said target timepoint as new first simulator inputs to said first simulator,

(c) back up said first simulator to said verified simulation time,

(d) generate new values for said first simulator outputs using said changed second simulator outputs as new first simulator inputs and said target timepoint as an ending time for the simulation,

(e) store said target timepoint as said verified simulation time and as said first simulator current simulation time,

(f) post said first simulator current simulation time, said verified simulation time and said first simulator output values as new second simulator inputs to said second simulator, and

(g) continue at step 3 until a predetermined final simulation time is reached;

(9) stop said second simulator program at said target timepoint (tt);

(10) post said target timepoint and said second simulator output values as new first simulator inputs to said first simulator;

(11) update said verified simulation time to said target timepoint (tt); and

(12) continue at step 3 until said predetermined final simulation time is reached.