Distributed pipeline memory architecture for a computer system with even and odd pids

• US 6,209,020 B1
• Filed: 09/20/1996
• Issued: 03/27/2001
• Est. Priority Date: 09/20/1996
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Harriman, Edward S. Jr., Ladwig, Geoffrey B., Angle, Richard L.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Rossi, Jeffrey Allen
• Application Number:
  US08/716,989
• Time in Patent Office: 1,649 Days
• Field of Search: 711/140, 395/800.23, 395/678, 395/376, 395/375, 709/108, 712/23, 712/200, 712/228
• US Class Current: 718/108
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A computer system architecture in which each processor has its own memory, strategically distributed along the stages of an execution pipeline of the processor, to provide fast access to often used information, such as the contents of the address and data registers, the program counter, etc. Memory storage is strategically located in close physical proximity to a stage in an execution pipeline at which memory is commonly or repeatedly accessed. Coupled to the pipeline at various stages are small memory cells for storing information that is consistently and repeatedly requested at that stage in the execution pipeline. The speed of the execution pipeline in a processor is critical to overall performance of the processor and the computer architecture of the present invention as a whole. To that end, the clock cycle time at which the pipeline is operated is increased as much as the operating characteristics of the logic and associated circuitry will allow. Generally, access times for memory are slower than the clock cycle times at which the pipeline logic can operate. Thus, there is a point of diminishing return at which increasing the clock cycle time of the pipeline is less advantageous if the pipeline must wait for memory access to complete. Thus, there is provided two sets of strategically located memory cells distributed along the execution pipeline of a processor, and alternately accesses the memory cells.

Claims

1. An execution pipeline having a plurality of stages concurrently executing a plurality of processes, the execution pipeline comprising:

a first memory cell located within a first stage and coupled to a first register;

a second memory cell located within the first stage and coupled to the first register;

a first selector located within the first stage and coupled to the first memory cell and the second memory cell, the first selector selecting one of the first memory cell and the second memory cell to provide data input to the first register;

a third memory cell located within a second stage and coupled to a second register;

a fourth memory cell located within the second stage and coupled to the second register; and

a second selector located within the second stage and coupled to the third memory cell and the fourth memory cell, the second selector selecting one of the third memory cell and the fourth memory cell to provide data input to the second register.

2. The execution pipeline of claim 1, wherein the plurality of processes are each identified by a process identification (PID).

3. The execution pipeline of claim 2, wherein the first selector selects one of the first memory cell and the second memory cell based on the PID of the process being executed by the first stage.

4. The execution pipeline of claim 3, wherein the first selector selects the first memory cell if the PID is odd and selects the second memory cell if the PID is even.

5. The execution pipeline of claim 2, wherein the second selector selects one of the third memory cell and the fourth memory cell based on the PID of the process being executed by the second stage.

6. The execution pipeline of claim 5, wherein the second selector selects the third memory cell if the PID is odd and selects the fourth memory cell if the PID is even.

7. An execution pipeline having a plurality of stages concurrently executing a plurality of processes, the execution pipeline comprising:

a plurality of registers coupled in communication;

a first memory cell located within a first stage and coupled to a first register, the first memory cell having stored therein data accessible by a first process being executed by the first stage;

a second memory cell located within the first stage and coupled to the first register, the second memory cell having stored therein data accessible by the first process;

a first selector located within the first stage and coupled to the first memory cell and the second memory cell, the first selector selecting one of the first memory cell and the second memory cell for access by the first process to provide data input to the first register;

a third memory cell located within a second stage and coupled to a second register, the third memory cell having stored therein data accessible by a second process being executed by the second stage;

a fourth memory cell located within the second stage and coupled to the second register, the fourth memory cell having stored therein data accessible by the second process; and

a second selector located within the second stage and coupled to the third memory cell and the fourth memory cell, the second selector selecting one of the third memory cell and the fourth memory cell for access by the second process to provide data input to the second register.

8. The execution pipeline of claim 7, wherein the plurality of processes are each identified by a process identification (PID).

9. The execution pipeline of claim 8, wherein the first selector selects one of the first memory cell and the second memory cell based on the PID of the process being executed by the first stage.

10. The execution pipeline of claim 9, wherein the first selector selects the first memory cell if the PID is odd and selects the second memory cell if the PID is even.

11. The execution pipeline of claim 8, wherein the second selector selects one of the third memory cell and the fourth memory cell based on the PID of the process being executed by the second stage.

12. The execution pipeline of claim 9, wherein the second selector selects the third memory cell if the PID is odd and selects the fourth memory cell if the PID is even.

13. A method for concurrently executing a plurality of processes within an execution pipeline having a plurality of stages, the method comprising:

storing data within a first memory cell which is accessible by a first process being executed by a first stage of the execution pipeline, the first memory cell located within the first stage and coupled to a first register;

storing data within a second memory cell which is accessible by the first process being executed by the first stage, the second memory cell located within the first stage and coupled to the first register;

selecting one of the first memory cell and the second memory cell for access by the first process to provide data input to the first register;

storing data within a third memory cell which is accessible by a second process being executed by a second stage of the execution pipeline, the second memory cell located within the second stage and coupled to a second register;

storing data within a fourth memory cell which is accessible by the second process being executed by the second stage, the fourth memory cell located within the second stage and coupled to the second register; and

selecting one of the third memory cell and the fourth memory cell for access by the second process to provide data input to the second register.

14. The method of claim 13 further comprising identifying each of the plurality of processes with a process identification (PID).

15. The method of claim 14, wherein selecting one of the first memory cell and the second memory cell is based on the PID of the process being executed by the first stage.

16. The method of claim 15, wherein the first memory cell is selected if the PID is odd and the second memory cell is selected if the PID is even.

17. The method of claim 14, wherein selecting one of the third memory cell and the fourth memory cell is based on the PID of the process being executed by the second stage.

18. The method of claim 17, wherein the third memory cell is selected if the PID is odd and the fourth memory cell is selected if the PID is even.