RAM data transmitting apparatus and method using a FIFO memory with three fullness flags

• US 6,209,047 B1
• Filed: 11/04/1996
• Issued: 03/27/2001
• Est. Priority Date: 11/03/1995
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ki-Hong
• Primary Examiner(s): Yoo, Do
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/743,072
• Time in Patent Office: 1,604 Days
• Field of Search: 395/877, 395/872, 365/189.05, 365/230.08, 710/57, 710/52, 710/53, 710/56, 710/60, 710/58
• US Class Current: 710/57
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A RAM data transmitting apparatus transmits data from a RAM to an external host via a first-in first-out (FIFO) memory having a given storage capacity. RAM data is sequentially written into the FIFO in response to the generation of a write enable signal. If the RAM data is written in a first area of the FIFO smaller than the FIFO storage area, a first flag is generated. If the RAM data is written in a second area of the FIFO (the second area being smaller than the storage capacity but larger than the first area), a second flag is generated. If no RAM data is written into or remains in the FIFO (the FIFO is empty), a third flag is generated. A controller is provided which generates the write enable signal from the time the first flag goes low until the second flag is generated, whereby the RAM data stored in the RAM is written in the first-in first-out memory. A data access circuit is provided to allow continuous accessing of the RAM data from the FIFO memory, beginning from the time the second flag is generated until the third flag is generated.

Claims

1. An apparatus for transmitting data comprising:

a first-in first-out (FIFO) memory having a storage capacity, for sequentially receiving data from a data storing unit in response to a write enable signal, wherein the FIFO memory has a first flag, a second flag, and a third flag as outputs, said first flag being generated when data from the data storing unit is written to a first portion of the FIFO memory, said first portion being smaller than said storage capacity of the FIFO memory, said second flag being generated when the data is written so as to fill a second portion of the FIFO memory, said second portion being smaller than said storage capacity of the FIFO memory and larger than said first portion, said third flag being generated when no data is contained in the FIFO memory;

controlling means for generating said write enable signal from when said first flag is generated until a time when said second flag is generated, wherein said write enable signal causes data stored in said data storing unit to be written into the FIFO memory, said controlling means disabling said write enable signal after a predetermined period after said second flag is generated; and

a host computer for continuously accessing the data written in said FIFO memory,

wherein a size of said first portion is adjustable by setting a setting value of said controlling means, so that the generation of said first flag and said second flag are adjustable depending on the size of said first portion, and said adjustable generation of said first flag allows said host computer to continuously access the data in the FIFO memory for a period of time after said second flag is generated and said predetermined period has elapsed, and subsequently until said third flag is generated, said period of time changing depending on said adjustable generation of said first flag and said second flag.

2. The apparatus as claimed in claim 1, wherein said second portion is smaller than said storage capacity.

3. The apparatus as claimed in claim 1, wherein said data storing unit is RAM.

4. An apparatus for transmitting data from a random access memory (RAM) comprising:

a first-in first-out (FIFO) memory having a storage capacity, for sequentially receiving RAM data from the RAM in response to a write enable signal, wherein the FIFO memory has a first flag, a second flag, and a third flag as outputs, said first flag being generated when RAM data from the RAM is written to a first portion of the FIFO memory, said first portion being smaller than said storage capacity of the FIFO memory, said second flag being generated when the RAM data is written so as to fill a second portion of the FIFO memory, said second portion being smaller than said storage capacity of the FIFO memory and larger than said first portion, said third flag being generated when no RAM data is contained in the FIFO memory;

RAM data transmission request signal generating means for generating a RAM data transmission request signal when said first flag is generated and until a time when said second flag is generated, and if said second flag is generated, blocking said RAM data transmission request signal until a first flag is again generated;

RAM controlling means for selecting RAM data to be written in the FIFO memory among the RAM data stored in the RAM in response to the generation of said RAM data transmission request signal and generating said write enable signal after the selection of the RAM data so as to write selected RAM data in said FIFO memory; and

data access means for continuously accessing the RAM data written in the FIFO memory,

wherein a size of said first portion is adjustable by setting a setting value of said RAM controlling means, so that the generation of said first flag and said second flag are adjustable depending on the size of said first portion, and said adjustable generation of said first flag allows said data access means to continuously access the RAM data in the FIFO memory after said second flag is generated, and during a period of time until subsequently said third flag is generated, said period of time changing depending on said adjustable generation of said first flag and said second flag.

5. The apparatus as claimed in claim 4, wherein said second portion is smaller than said storage capacity.

6. A method of writing RAM data stored in a RAM into a first-in first-out memory having a storage capacity and if there is a request of an access from data access means, transmitting the RAM data written in said first-in first-out memory to said data access means, said method comprising the steps of:

generating a first flag when the RAM data is written in a first area of the first-in first-out memory;

generating a second flag when the RAM data is written so as to fill a second area of the first-in first-out memory, said second area being larger than said first area and smaller than said storage capacity;

generating a third flag when no RAM data is written in the first-in first-out memory;

writing the RAM data stored in said RAM into the first-in first-out memory when said first flag is generated and until said second flag is generated;

accessing the RAM data written in said first-in first-out memory to said data access means, when said second flag is generated and in response to an access request of said data access means; and

halting the accessing step when said third flag is generated, and

adjusting a size of said first area so that the generation of said first flag and said second flag is adjustable depending on the size of said first area, and said adjustable generation of said first flag allows said data access means to continuously access the data in the first-in-first-out memory in said accessing step from a period of time after said second flag is generated until said third flag is generated and said halting step is conducted, said period of time changing depending on said adjusting step and said adjustable generation of said first flag and said second flag.

7. The method as claimed in claim 6, wherein said second area is smaller than said storage capacity.