Mechanism for optimizing generation of commit-signals in a distributed shared-memory system

• US 6,209,065 B1
• Filed: 10/24/1997
• Issued: 03/27/2001
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Gharachorloo, Kourosh, Steely, Simon C. Jr., Van Doren, Stephen R., Sharma, Madhumitra
• Primary Examiner(s): ELLIS, KEVIN L
• Application Number:
  US08/957,230
• Time in Patent Office: 1,250 Days
• Field of Search: 711/118, 711/119, 711/141, 711/144, 711/145, 711/146, 711/147, 711/148, 711/153, 711/130, 711/150, 711/151, 711/152, 711/167
• US Class Current: 711/150
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The mechanism generally comprises a structure that indicates whether the memory reference operation affects other processors of other nodes of the multiprocessor system. An ordering point of the local node generates an optimized commit-signal when the structure indicates that the memory reference operation does not affect the other processors.

Claims

1. A mechanism for optimizing generation of a commit signal in response to a local memory reference operation issued by a first processor in a distributed shared memory multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes, each node comprising a local switch interconnecting at least one local processor with the hierarchical switch, the mechanism comprising:

a structure for optimizing the generation of the commit signal, the optimized commit signal being generated by control logic at a first node associated with the first processor instead of at the hierarchical switch, the structure indicating whether the memory reference operation issued by the first processor affects any non-local processor of the system, the optimized commit signal transmitted to the first processor to thereby obviate transmission of the signal to the hierarchical switch.

2. The mechanism of claim 1 wherein the memory reference operation affects a non-local processor if the operation has an invalidate component generated by an ordering point of the local switch.

3. The mechanism of claim 2 wherein the invalidate component is a probe-type command and wherein each processor employs a cache apportioned into a plurality of cache lines.

4. The mechanism of claim 3 wherein the probe-type command is transmitted over the hierarchical switch to invalidate copies of data stored in the caches of the processors.

5. The mechanism of claim 4 wherein the structure is a loopcomsig table configured to monitor outstanding probe-type commands from the first node.

6. The mechanism of claim 5 wherein the loopcomsig table comprises a plurality of entries, each entry including an address field and a plurality of status bits.

7. The mechanism of claim 6 wherein the address field stores an address of a cache line for a probe-type command that is outstanding from the first node.

8. The mechanism of claim 7 wherein the status bits reflect one of a status of the outstanding probe-type command and a property of the memory reference operation.

9. The mechanism of claim 8 wherein one of the status bits is a valid bit indicating whether an allocated entry is valid, wherein a valid indication reflects a probe-type command having with outstanding probe acknowledgements.

10. A method for optimizing generation of a commit signal in response to a local memory reference operation issued by a first processor of a first node in a distributed shared memory multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes, each node comprising a local switch interconnecting at least one local processor with the hierarchical switch, each processor employing a cache apportioned into a plurality of cache lines, the method comprising the steps of:

providing a data structure at the first node that optimizes generation of the commit signal by storing information that indicates whether the memory reference operation issued by the first processor affects any non-local processor of the system, the memory reference operation affecting a non-local processor if the operation has a probe generated by an ordering point of the local switch at the first node;

creating an entry in the data structure for the memory reference operation in response to the operation having a probe that is transmitted to and currently outstanding at the hierarchical switch, the probe configured to invalidate a copy of data associated with the operation that is stored in the cache of a non-local processor, the entry storing an address of a cache line for the outstanding probe; and

optimizing generation of the commit signal at the first node when there is no entry in the data structure associated with the memory reference operation.

11. The method of claim 10 wherein the step of optimizing generation comprises the steps of:

generating the commit signal at control logic of the first node; and

transmitting the commit signal to the first processor, thereby obviating transmission of the generated commit signal to the hierarchical switch.

12. The method of claim 11 wherein the commit signal is a type 0 commit signal.

13. The method of claim 12 further comprising the step of, in response to transmitting a probe to the hierarchical switch, totally ordering the probe at the hierarchical switch.

14. The method of claim 13 further comprising the step of, in response to the step of totally ordering, returning an invalidate acknowledgment from the hierarchical switch.

15. The method of claim 14 further comprising the step of, in response to the step of returning, removing the entry from the data structure.