Address re-mapping for memory module using presence detect data
First Claim
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1. A memory module comprising:
- a plurality of memory devices associated with the memory module;
each of said memory devices being configured in M banks; and
a logic circuit for configuring the memory module to operate in a programmable addressing mode;
said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address signals corresponding to N bank memory devices where M and N are integers and can be different;
said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device where M and N are different; and
a non-volatile memory for storing initial presence detect (PD) data;
a volatile memory for storing modified PD data that corresponds to a requested mode of operation of a memory module input by a system controller; and
a bus controller for interfacing the memory module with the system controller.
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Abstract
A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device.
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Citations
25 Claims
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1. A memory module comprising:
- a plurality of memory devices associated with the memory module;
each of said memory devices being configured in M banks; and
a logic circuit for configuring the memory module to operate in a programmable addressing mode;
said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address signals corresponding to N bank memory devices where M and N are integers and can be different;
said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device where M and N are different; and
a non-volatile memory for storing initial presence detect (PD) data;
a volatile memory for storing modified PD data that corresponds to a requested mode of operation of a memory module input by a system controller; and
a bus controller for interfacing the memory module with the system controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
- a plurality of memory devices associated with the memory module;
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17. A computer system comprising:
- a system controller;
a memory module comprising a plurality of memory devices on the module, and a memory module logic circuit for configuring the memory module to operate in a programmable addressing mode;
each of said memory devices being configured with M banks;
said logic circuit receiving a number of address inputs and a number of bank address signals from said system controller with said address inputs and bank address signals corresponding to N bank memory devices wherein M and N are integers and can be different;
said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device wherein M and N are different; and
wherein said system controller negotiates an addressing mode of the memory module by reading and writing presence detect (PD) data of the memory module. - View Dependent Claims (18, 19, 20, 21)
- a system controller;
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22. A method for system control of an intelligent memory module, comprising:
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a) reading presence detect (PD) data from a non-volatile memory on the module;
b) writing modified PD data to a volatile memory based on a requested addressing mode; and
c) controlling transfer of said PD data between the memory module and a system controller based on which memory stores up-to-date PD data. - View Dependent Claims (23, 24)
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25. A method for using an M bank memory device in a computer system that has N bank addressing wherein and M and N are integers and are different, comprising the steps of:
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a) inputting address signals from a system controller to a logic circuit, said address signals including a number of address inputs and a number of bank address signals;
b) re-mapping at least one of said address inputs as an additional bank address signal including the step of connecting a highest order address input received from the system controller to one of the bank address signals of the memory device; and
c) providing said address inputs, said bank address signals and said additional bank address signals as inputs to the memory device.
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Specification