Address re-mapping for memory module using presence detect data

• US 6,209,074 B1
• Filed: 04/28/1998
• Issued: 03/27/2001
• Est. Priority Date: 04/28/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dell, Timothy Jay, Kellogg, Mark William
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US09/067,549
• Time in Patent Office: 1,064 Days
• Field of Search: 711/5, 711/170, 711/202, 711/171, 711/172, 365/230.04
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration

Abstract

A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device.

Claims

1. A memory module comprising:

a plurality of memory devices associated with the memory module;

each of said memory devices being configured in M banks; and

a logic circuit for configuring the memory module to operate in a programmable addressing mode;

said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address signals corresponding to N bank memory devices where M and N are integers and can be different;

said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device where M and N are different; and

a non-volatile memory for storing initial presence detect (PD) data;

a volatile memory for storing modified PD data that corresponds to a requested mode of operation of a memory module input by a system controller; and

a bus controller for interfacing the memory module with the system controller.

2. The memory module of claim 1 wherein said system controller operates to read the initial PD data and to write modified PD data to said volatile memory;

said modified PD data corresponding to a system controller requested addressing mode of the module;

said logic circuit operating to accept said modified PD data when the requested addressing mode is available in the module.

3. The memory module of claim 2 wherein said logic circuit operates to control said modified PD data transfer to the system controller from said volatile and non-volatile memories based on which memory stores up-to-date PD data.

4. The memory module of claim 1 wherein said initial PD data is serially accessed with a serial bus controller that interfaces with the system controller.

5. The memory module of claim 1 wherein said non-volatile memory comprises an EEPROM that stores original serial PD data.

6. The memory module of claim 1 wherein said logic circuit comprise an ASIC (application specific integrated circuit) logic device and includes a non-volatile memory that stores original serial PD data.

7. The memory module of claim 1 comprising an I2C bus controller and an I2C bus;

said system controller reading serial PD data from said non-volatile memory after memory power up, and determining compatibility of memory module addressing functions with system requirements.

8. The memory module of claim 1 wherein said system controller writes said modified PD data to said volatile memory that corresponds to a desired addressing mode of the memory module based on system requirements.

9. The memory module of claim 8 wherein said logic circuit operates to accept said modified PD data when the corresponding desired addressing mode is available in the module.

10. The memory module of claim 9 wherein said logic circuit operates to control PD data transfer to the system controller from said volatile and non-volatile memories based on which memory stores up-to-date PD data, said logic circuit setting a flag bit for each modified PD data entry so that PD data that has been modified is read by the system controller from said volatile memory.

11. The memory module of claim 1 comprising a serial bus and serial bus controller for interfacing a system controller with the module so that the system controller can read and write serial PD data of the module to negotiate an addressing mode for the module.

12. The memory module of claim 1 wherein M is greater than N.

13. The memory module of claim 12 wherein said logic circuit detects an address input from a system memory controller and re-maps and saves said address input as a bank address signal.

14. The memory module of claim 12 wherein said logic circuit re-maps an address input into a bank address signal to provide N bank addressing using M bank SDRAM devices.

15. The memory module of claim 1 wherein at least one of said memory devices comprises a synchronous DRAM (SDRAM) memory device.

16. The memory module of claim 1 wherein said logic circuit connects a highest order address input from the memory controller to said additional bank address signal of a memory device being addressed.

17. A computer system comprising:

a system controller;

a memory module comprising a plurality of memory devices on the module, and a memory module logic circuit for configuring the memory module to operate in a programmable addressing mode;

each of said memory devices being configured with M banks;

said logic circuit receiving a number of address inputs and a number of bank address signals from said system controller with said address inputs and bank address signals corresponding to N bank memory devices wherein M and N are integers and can be different;

said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device wherein M and N are different; and

wherein said system controller negotiates an addressing mode of the memory module by reading and writing presence detect (PD) data of the memory module.

18. The computer system of claim 17 wherein bus controller comprises a serial bus controller and said system controller operates to read and write serial PD data of the memory module.

19. The computer system of claim 17 wherein said memory module comprises a volatile memory that stores modified PD data written by said system controller that corresponds to a requested addressing mode, and a non-volatile memory that stores initial PD data, said volatile and non-volatile memories being operatively controlled by said logic circuit.

20. The computer system of claim 19 wherein said logic circuit accepts said modified PD data when the requested addressing mode is available in the module, and controls a transfer of PD data from said volatile and non-volatile memories based on which memory stores up-to-date data with respect to each PD data entry.

21. The computer system of claim 17 wherein said logic circuit re-maps addressing signals for said memory module to provide N bank addressing using M bank memory chips in said memory module.

22. A method for system control of an intelligent memory module, comprising:

a) reading presence detect (PD) data from a non-volatile memory on the module;

b) writing modified PD data to a volatile memory based on a requested addressing mode; and

c) controlling transfer of said PD data between the memory module and a system controller based on which memory stores up-to-date PD data.

23. The method of claim 22 wherein a logic circuit on the module re-maps an address input to a bank address signal to provide N bank addressing using M bank memory chips.

24. The method of claim 22 wherein the logic circuit receives a highest order address signal and re-maps and saves said address input as said bank address signal.

25. A method for using an M bank memory device in a computer system that has N bank addressing wherein and M and N are integers and are different, comprising the steps of:

a) inputting address signals from a system controller to a logic circuit, said address signals including a number of address inputs and a number of bank address signals;

b) re-mapping at least one of said address inputs as an additional bank address signal including the step of connecting a highest order address input received from the system controller to one of the bank address signals of the memory device; and

c) providing said address inputs, said bank address signals and said additional bank address signals as inputs to the memory device.