General purpose programmable accelerator board

• US 6,209,077 B1
• Filed: 12/21/1998
• Issued: 03/27/2001
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Robertson, Perry J., Witzke, Edward L.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/217,099
• Time in Patent Office: 827 Days
• Field of Search: 326/39, 326/41, 326/93, 712/15, 712/17, 712/10, 712/11, 710/129, 710/246, 710/62, 710/64, 710/37, 708/230, 708/232, 708/233, 345/503, 711/167, 711/151
• US Class Current: 712/17
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Claims

1. A general purpose accelerator board comprising:

a programmable logic device having input/output ports and control signal ports;

a plurality of memory blocks operationally connected to said input/output ports;

bus interface means for communicating data between said memory blocks and devices external to said board; and

dynamic programming means for providing logic to said programmable logic device to be executed on data in said memory blocks.

2. The board of claim 1 wherein said bus interface means additionally comprises means for communicating logic instructions between said programmable logic device and devices external to said board.

3. The board of claim 1 additionally comprising control logic means operationally connected to said control signal ports.

4. The board of claim 1 wherein said board comprises a PCI board.

5. The board of claim 1 wherein said programmable logic device is configurable to perform each of the computational transforms selected from the group consisting of discrete Fourier transforms, convolutions, encryption, decryption, filtering, image processing, and signal processing.

6. The board of claim 1 wherein said board is configurable to execute standard system functions and dynamical linked libraries for a device external to said board.

7. The board of claim 1 wherein said bus interface means is capable of extracting a subset of data from a memory block during execution of said logic.

8. The board of claim 1 wherein said plurality of memory blocks comprises a multiple of two memory blocks.

9. A general purpose computer acceleration method comprising the steps of:

a) providing a programmable logic device having input/output ports and control signal ports;

b) providing a plurality of memory blocks operationally connected to said input/output ports;

c) providing bus interface means for communicating data between the memory blocks and devices external to the board;

d) dynamically providing logic to the programmable logic device; and

e) moving data from one memory block to another memory block through the programmable logic device, said programmable logic device transforming said data in response to said logic.

10. The method of claim 9 wherein the step of providing bus interface means additionally comprises providing means for communicating logic instructions between the programmable logic device and external devices.

11. The method of claim 9 additionally comprising the step of providing control logic means operationally connected to said control signal ports.

12. The method of claim 9 wherein the providing steps comprise providing to a PCI board.

13. The method of claim 9 wherein said programmable logic device performs a computational transform selected from the group consisting of discrete Fourier transforms, convolutions, encryption, decryption, filtering, image processing, and signal processing.

14. The method of claim 9 additionally comprising the step of executing standard system functions and dynamical linked libraries for an external device.

15. The method of claim 9 wherein the step of providing bus interface means comprises providing means capable of extracting a subset of data from a memory block during execution of the logic.

16. The method of claim 9 wherein the step of providing a plurality of memory blocks comprises providing a multiple of two memory blocks.